GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER-III (NEW) EXAMINATION — SUMMER 2019
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Subject Code: 2130306 Date: 18/06/2019Subject Name: Fundamentals of Digital Design
Time: 02:30 PM TO 05:00 PM Total Marks: 70
Instructions:
- Attempt all questions.
- Make suitable assumptions wherever necessary.
- Figures to the right indicate full marks.
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MARKS
Q.1 (a) Perform BCD subtraction using 9’s complement for : 03
(151.6 - 89.7)10
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(b) Draw logic symbols for Bubbled-AND & NOR gate. Prove that 04
both give same output using truth table.
(c) Draw AOI logic for (A’B + AB’) and convert it to NAND and NOR 07
logic.
Q.2 (a) Which are called Universal Logic Gates? Explain with one example 03
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why?(b) Expand A(B’ + A)B to maxterms and minterms. 04
(c) Reduce the following expression using K-map and implement it in 07
universal logic:
?m(0,1,2,3,4,6,8,9,10,11)
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OR
(c) Minimize the following expression using tabulation method: 07
?m(0,1,2,8,9,15,17, 21, 24,25,27,31)
Q.3 (a) Explain Half-subtractor in detail with equations and NOR logic 03
circuit.
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(b) Explain 4x1 multiplexer in detail. 04
(c) Design 2-bit parallel adder using Look-Ahead Carry. 07
OR
Q.3 (a) Explain Half-adder in detail with equations and NAND logic circuit. 03
(b) Explain 4-bit ripple adder with block diagram. 04
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(c) Design a combination circuit where input given at D1 of 2x1 07
multiplexer can be displayed at D3 output of 1x4 demultiplexer.
Q.4 (a) What are Active-High and Active-Low configurations? Explain in 03
detail.
(b) Explain edge triggered D Flip flop. 04
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(c) Explain NAND gate S-R latch and NOR Gate S-R latch with truth 07
table and Logic circuit.
OR
Q.4 (a) List different applications of Flip-Flops. 03
(b) Explain edge triggered T Flip flop. 04
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(c) Explain edge triggered JK Flip-flop for Active-High and Active- 07
Low configuration.
Q.5 (a) For DAC define: 03
(1) Resolution, (2)Settling time (3) Offset Voltage
(b) Explain Programmable Array Logic (PAL) with basic circuit 04
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structure.(c) Explain Serial-IN Serial-OUT shift register. 07
Q.5 (a) List types of A/D convertors. 03
(b) Using simplified connection method in PLA circuits draw circuit 04
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for following functions:F1=AB’C+A’B’C+AC
F2=ABC+AB’+C
(c) Explain BCD to Seven Segment decoder for common-cathode LED 07
display.
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