Download GTU BE/B.Tech 2019 Summer 6th Sem Old 161004 Vlsi Technology And Design Question Paper

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Subject Code: 161004

GUJARAT TECHNOLOGICAL UNIVERSITY

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SEMESTER-VI(OLD) - EXAMINATION - SUMMER 2019

Subject Name: VLSI Technology And Design

Time: 10:30 AM TO 01:00 PM

Instructions:

1. Attempt all questions.

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2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

1. Q.1
   1. Draw & explain Y Chart. (07)
   2. Explain basic steps of LOCOS isolation with necessary diagram. (07)

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2. Q.2
   1. Derive the current equation for an n channel MOSFET transistor operating in the saturation region. (07)
   2. Calculate the threshold voltage V_T0, for a polysilicon gate n-channel MOS transistor, with the following parameters: Substrate doping density N_a = 10¹⁶ cm^-3, polysilicon gate doping density N_p=2x10²⁰ cm^-3, gate oxide thickness t_ox = 500Å, and oxide interface fixed charge density N_ox = 4x10¹⁰ cm^-2. (KT/q=0.026V, n_i= 1.45x10¹⁰ cm^-3, e₀= 8.85x10^-14 F/cm, e_si= 11.7x e₀ F/cm, e_ox= 3.97x e₀ F/cm) (07)
      OR
      Discuss different operating regions of the MOSFET and derive the equation for the depth of depletion region width. (07)

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3. Q.3
   1. Draw the inverter circuit with resistive type load. Derive critical voltages points V_OH, V_OL, V_IH and V_IL. (07)
   2. Consider a CMOS inverter circuits with the following parameters: V_DD= 3.3V, V_T0n = 0.6V, V_T0p = -0.7V, k_n = 200uA/v² , k_p = 80uA/v². Calculate the noise margin of the circuit. (07)
      OR
      Explain Elmore delay calculation method for complex RC network. Derive the formula for Elmore delay T_pn. (07)

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4. Q.4
   1. Consider a resistive load inverter circuit with V_DD = 5v, k' = 20uA/V², V_T0 = 0.8v, R_L =200kO and W/L =2: Calculate the critical voltages V_OH, V_OL, V_IH and V_IL on the VTC and find the noise margins of the circuits. (07)
   2. Realize the Boolean function F= [(A(D+E)+BC]’ using NMOS depletion load. (07)
5. Q.5
   1. Explain in detail CMOS SR latch circuit based on NOR2. (07)
      OR
      

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      Implement F= A XOR B using eight transistor CMOS transmission gate. (07)
   2. Draw CMOS negative edge triggered master slave D flip-flop & explain its working. (07)

1. Q.5
   1. Explain the basic principal of pass transistor circuit. Explain Logic ‘1’ transfer and logic ‘0’ transfer. (07)
   2. What is latch up? Mention the causes of the latch-up and its prevention techniques for CMOS inverter. (07)
      

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      OR
      What is the need for voltage bootstrapping? Explain dynamic voltage bootstrapping circuit with necessary mathematical analysis. (07)

Explain in detail: Adhoc testable design techniques. (07)

Date: 20/05/2019

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Total Marks: 70

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