Download GTU BE/B.Tech 2018 Winter 6th Sem New 2161101 Vlsi Technology And Design Question Paper

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Subject Code: 2161101

GUJARAT TECHNOLOGICAL UNIVERSITY

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Instructions:

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1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

1. 1. Explain VLSI Design flow using Y-chart. [03]
   2. Discuss physical parameters affecting the threshold voltage of MOS structure. [04]

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   3. Derive the MOSFET drain current equation while MOSFET is operating in linear region using GCA. [07]
2. 1. Draw mask layout of the CMOS Inverter and indicate various terms. [03]
   2. In CMOS inverter circuit, enhancement type MOSFET devices are used and if Vbpp is reduced below Vron+ [V1o,p|, explain how the output voltage will follow the change in input voltage. Draw VTC and explain its behavior. [04]
   3. Discuss fabrication process of n-channel MOSFET in detail. [07]

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   OR
   1. Draw Resistive-load inverter using n-channel MOSFET. Derive expressions of critical voltages VoL Voun, ViL and ViH of Resistive-load inverter. [03]
   2. Compare Semi-custom and Full custom VLSI design style. [04]
   3. What do you mean by MOSFET Scaling? Explain Constant-field Scaling. [07]
3. 1. “The average power dissipation of the CMOS Inverter is proportional to switching frequency.” Explain it with necessary mathematical analysis. [03]

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   2. Give comparison between FPGA and CPLD. [04]
   3. Describe Accumulation and Inversion process for the MOS system under external bias. [07]
   OR
   1. Derive expression of TonL for CMOS Inverter where input is ideal step input. [03]
   2. Explain CMOS Ring Oscillator circuit in brief. [04]
   3. Draw different representations of the CMOS Transmission Gate. Implement 2x1 Multiplexer circuit using two CMOS TGs and one inverter. [07]

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4. 1. Explain cascading problem observed in dynamic CMOS logic. What are the different approaches to solve this problem? [03]
   2. Discuss VTC of CMOS Inverter with operating region. [04]
   3. Implement Boolean function Z = AB+C(D+E) using CMOS logic circuit [07]
   OR
   1. Discuss need of Voltage Bootstrapping and explain dynamic Voltage Bootstrapping with necessary mathematical analysis. [03]

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   2. List out possible physical, electrical and logical faults observed at Chip Testing. [04]
   3. Define Latch-up. Enlist guidelines for avoiding Latch-up. [07]
5. 1. Explain D latch with CMOS implementation. [03]
   2. Draw NAND gate based CMOS SR latch circuit. [04]

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   3. Explain various Clock Distribution Networks. [07]
   OR
   1. Explain Ad Hoc Testable Design Techniques. [07]

Date: 30/11/2018

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