Download GTU BE/B.Tech 2018 Winter 6th Sem Old 161004 Vlsi Technology And Design Question Paper

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Subject Code: 161004

GUJARAT TECHNOLOGICAL UNIVERSITY

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BE - SEMESTER-VI (OLD) EXAMINATION - WINTER 2018

Subject Name: VLSI Technology And Design

Time: 02:30 PM TO 05:00 PM

Instructions:

1. Attempt all questions.

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2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

1. Q.1 (a) Explain VLSI design flow. MARKS 07

2. Q.1 (b) Write short note on CMOS Transmission Gates. MARKS 07

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3. Q.2 (a) Describe fabrication process of MOSFET. MARKS 07

4. Q.2 (b) Define following operating regions for the MOS system with suitable energy band diagrams: (a) Accumulation (b) Depletion (c) Inversion MARKS 07

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5. Q.3 (a) Derive the expression of threshold voltage of an n-channel MOSFET. MARKS 07

6. Q.3 (b) Draw CMOS inverter circuit, its VTC and derive V_g and V_iL. MARKS 07

7. Q.4 (a) Consider a CMOS inverter circuit with the following parameters: V_DD =3.3 V, V_ton=0.6 V V_top =- 0.7 V, K_n =200 µA/V² , K_p = 80 µA/V² . Calculate the noise margins of the circuit. MARKS 07

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8. Q.4 (b) Draw resistive load inverter circuit and derive V_on, V_or, V_iL, and V_iH. MARKS 07

9. Q.5 (a) Design a resistive-load inverter with R'= 1 kO, such that V_oL =0.2 V. The enhancement-type nMOS driver transistor has the following parameters V_DD =5 .0 V V_to=1.V µ_nC_ox = 30 µA/V² Determine the required aspect ratio, W/L. MARKS 07

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10. Q.5 (b) Define propagation delay and derive the expression for t_PHL for CMOS Inverter. Assume ideal step as an input to CMOS Inverter. MARKS 07

11. Q.3 (a) Explain the basic principle of pass transistor circuit. Explain logic ‘1’ transfer and logic ‘0’ transfer. MARKS 07

12. Q.3 (b) Write a note on CMOS Ring Oscillator circuit. MARKS 07

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13. Q.4 (a) Explain the dynamic CMOS logic (Precharge — Evaluation) and discuss the cascading problem in dynamic CMOS logic. MARKS 07

14. Q.4 (b) Implement following Boolean logic equation using Transmission Gate (TG). Y =AB+ A’C’+AB’C MARKS 07

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15. Q.5 (a) Discuss the on-chip clock generation and distribution. MARKS 07

16. Q.5 (b) Explain Built In Self Test (BIST) in detail. MARKS 07

17. Q.5 (a) Give comparison between FPGA and CPLD. MARKS 07

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Date: 27/11/2018

Total Marks: 70