Download PTU B.Tech 2021 Jan ECE 7th Sem 71912 Cmos Based Design Question Paper

Download PTU (Punjab Technical University) B.Tech (Bachelor of Technology) / BE (Bachelor of Engineering) 2021 January ECE 7th Sem 71912 Cmos Based Design Previous Question Paper

Roll No.
Total No. of Pages : 02
Total No. of Questions : 18
B.Tech. (ECE) (Sem.?7)
CMOS BASED DESIGN
Subject Code : BTEC-908
M.Code : 71912
Time : 3 Hrs. Max. Marks : 60
INST RUCT IONS T O CANDIDAT ES :
1 .
SECT ION-A is COMPULSORY cons is ting of TEN questions carrying TWO marks
each.
2 .
SECT ION-B c ontains F IVE questions c arrying FIVE marks eac h and s tud ents
have to atte mpt any FOUR q ues tions.
3 .
SECT ION-C contains THREE questions carrying T EN marks e ach and s tudents
have to atte mpt any T WO questio ns.
SECTION-A
Write briefly :
1)
Design a 3 input NOR gate using CMOS inverter.
2)
Explain pull-up and pull-down networks for CMOS logic.
3)
Draw drain current vs. voltage chart for MOS transistor.
4)
Give the steps of CMOS processing.
5)
Define photolithography.
6)
Define propagation delay time.
7)
What do you mean by linear delay model?
8)
Define circuit family.
9)
Explain glitching transitions.
10) Define the term sizing.
1 | M - 7 1 9 1 2
( S 2 ) - 7 1 5

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SECTION-B
11) Give various design layout rules.
12) Explain the process of Photo masking with a negative resist.
13) Enlist the advantages and disadvantages of scaling.
14) Using static CMOS, design Bubble pushing to convert ANDs and ORs to NANDs and
NORs.
15) Explain the optimization of Domino logic.
SECTION-C
16) Explain all the steps of fabrication process with diagrams.
17) Explain Gate and shallow source/drain formation.
18) Explain transistor and interconnect scaling.
NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any
page of Answer Sheet will lead to UMC against the Student.
2 | M - 7 1 9 1 2
( S 2 ) - 7 1 5

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