FirstRanker Logo

FirstRanker.com - FirstRanker's Choice is a hub of Question Papers & Study Materials for B-Tech, B.E, M-Tech, MCA, M.Sc, MBBS, BDS, MBA, B.Sc, Degree, B.Sc Nursing, B-Pharmacy, D-Pharmacy, MD, Medical, Dental, Engineering students. All services of FirstRanker.com are FREE

📱

Get the MBBS Question Bank Android App

Access previous years' papers, solved question papers, notes, and more on the go!

Install From Play Store

Download PTU B.Tech 2021 Jan ECE 7th Sem 71912 Cmos Based Design Question Paper

Download PTU (Punjab Technical University) B.Tech (Bachelor of Technology) / BE (Bachelor of Engineering) 2021 January ECE 7th Sem 71912 Cmos Based Design Previous Question Paper

This post was last modified on 26 June 2021

PTU B.Tech 2021 January Previous Question Papers || PTU Punjab Technical University


Roll No. ____________________ Total No. of Pages : 02

Total No. of Questions : 18 B.Tech. (ECE) (Sem.-7)

CMOS BASED DESIGN

--- Content provided by‍ FirstRanker.com ---

Subject Code : BTEC-908

M.Code : 71912

Time : 3 Hrs. Max. Marks : 60

INSTRUCTIONS TO CANDIDATES :

  1. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each.
  2. --- Content provided by​ FirstRanker.com ---

  3. SECTION-B contains FIVE questions carrying FIVE marks each and students have to attempt any FOUR questions.
  4. SECTION-C contains THREE questions carrying TEN marks each and students have to attempt any TWO questions.

SECTION-A

Write briefly :

  1. Design a 3 input NOR gate using CMOS inverter.
  2. --- Content provided by‌ FirstRanker.com ---

  3. Explain pull-up and pull-down networks for CMOS logic.
  4. Draw drain current vs. voltage chart for MOS transistor.
  5. Give the steps of CMOS processing.
  6. Define photolithography.
  7. Define propagation delay time.
  8. --- Content provided by‌ FirstRanker.com ---

  9. What do you mean by linear delay model?
  10. Define circuit family.
  11. Explain glitching transitions.
  12. Define the term sizing.

SECTION-B

--- Content provided by FirstRanker.com ---

  1. Give various design layout rules.
  2. Explain the process of Photo masking with a negative resist.
  3. Enlist the advantages and disadvantages of scaling.
  4. Using static CMOS, design Bubble pushing to convert ANDs and ORs to NANDs and NORs.
  5. Explain the optimization of Domino logic.
  6. --- Content provided by⁠ FirstRanker.com ---

SECTION-C

  1. Explain all the steps of fabrication process with diagrams.
  2. Explain Gate and shallow source/drain formation.
  3. Explain transistor and interconnect scaling.

NOTE: Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.

--- Content provided by‍ FirstRanker.com ---

FirstRanker.com



This download link is referred from the post: PTU B.Tech 2021 January Previous Question Papers || PTU Punjab Technical University

--- Content provided by​ FirstRanker.com ---