Roll No. _________________________ Total No. of Pages : 02
Total No. of Questions: 18
B.Tech. (IT) (2018 Batch) (Sem.-3)
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COMPUTER ARCHITECTURE
Subject Code: BTES-302-18
M.Code: 76394
Time: 3 Hrs. Max. Marks: 60
INSTRUCTIONS TO CANDIDATES :
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- SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each.
- SECTION-B contains FIVE questions carrying FIVE marks each and students have to attempt any FOUR questions.
- SECTION-C contains THREE questions carrying TEN marks each and students have to attempt any TWO questions.
SECTION-A
Answer briefly :
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- What are addressing mode used for?
- How a number is represented using floating point representations?
- Explain pros and cons of RISC architecture.
- What are different layers of memory organization?
- What is role of interrupts?
- What is DMA controller?
- What is the difference between hardware and software interrupts?
- What are the disadvantages of multi-level cache memory?
- Differentiate between write back and write through policies.
- Why Optimal Page Replacement Algorithm is practically impossible to implement?
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SECTION-B
- Explain in detail differences between hardwired and micro-programmed control unit design.
- Create the circuit diagram of full adder using two half adders.
- Explain parallel processing. What are the challenges in achieving parallel processing?
- Differentiate between primary and secondary memory with examples.
- Write short note on I/O interfaces.
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SECTION-C
- Explain various stages in instruction pipelining. Discuss in detail methods to handle control hazards.
- Explain cache mapping techniques wiz, Direct, associative and Set-Associative mapping.
- Explain addressing modes in 8085 microprocessor with examples:
- Immediate addressing mode
- Register addressing mode
- Direct addressing mode
- Register indirect addressing mode
- Implied addressing mode
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NOTE: Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.
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