Download Visvesvaraya Technological University (VTU) BEB.Tech (Bachelor of Engineering/ Bachelor of Technology) 2020 January [folder1] 3rd Sem 17EC34 Digital Electronics Previous Question Paper
USN
17EC34
Third Semester B.E. Degree Examination, Dec.2019/Jin.2020
Digital Electronics
Time: 3 hrs. Max. Marks: 100
Note: Answer any FIVE full questions, choosing ONE full question from each module.
U
s
P Module1
? 1 a. Express the following functions into a canonical form:
,.,
0 f
i
= a + be + bcd
ii) f2 = a(b + c) (b + c + d)
_
?
,,
(08 Marks)
t.11
cz b. Represent the number of days in a month for a nonleap year by a truth cable, indicating the
c.=
output of a invalid inputs if any by '0'. (06 Marks)
dijor j;
?
6
.
S3 c. Simplify the given function using Kmap method
ta 0
c oc,
f(abcd) = Ern (1, 2, 4, 11, 13, 14, 15) +d (0, 5, 7, 8, 10).
*E +
(06 Marks)
. cs,
c *C 71
E d)
L.. .
OR
,i, c
.c o
2 a. Find all prime implicants of the function using Quineindustry method and verify the same
=
by Kmap method .f(abcd) = Em (0, 2, 3, 4, 8, 10, 12, 13, 14) (10 Marks)
ai ti
,
c
. a
0 b.
Find minimal sum and minimal product for the incomplete Boolean function using Kmap

2
.7...
1:1 5
f(abcd) = Em(6, 7, 9, 10, 13) + d E(1, 4, 5, 11, 15). (10 Marks)
cr
U 4.)
7 O
:
CZ
0
c     
Module2
0
C
ct
3 a. Design two bit magnitude comparator. (10 Marks)
. ,
74 b. Design 4:2 priority encoder with a valid output where highest priority is given to the highest
45 73
bit position. (10 Marks)
il
0
O ,.
a B.
OR
0 F,
, ,
d
4 a. Design and realize the Boolean function using IC74139.
6 .2 fl(ab) = E(0, 2), f2(abc) = E(1, 3, 5, 7). (05 Marks)
a.) 'F v ;
b. Explain how look ahead carry adder circuit will reduce the propagation delay with the help
.
,
..
0
.
c 
c t.
of carry propagate and carry generate function. (08 Marks)
L Q.)
E
1
/
> , c ? 
C. Implement the Boolean function f(abcd) = E(0, 2, 4, 5, 7, 9, 10, 14) using multiplexers with
0
? to two 4:1 MUX with variable 'a' and 'b' are connected to their select lines in first level and
E.
c
t 
one 2:1 MUX with variable 'c' connected to its select line in second level. (07 Marks)
c'
3
E
0
. >,
6
.,
Module3
_4 csi
5 a. With the help of logic circuit and waveforms. Explain switch bouncing applications using
? ?
0
0,
SR latch. (06 Marks)
z
b.
Write the characteristics equation for SR, JK flip flop. (06 Marks)
,:. c.
With neat logic diagram, and waveform. Explain the operation of masterslave JK flipflop.
?_
,,,.,?
...., . ...
(08 Marks)
;,. ... . ..
1 of 2 ..'
/N .
'
/ ... /
,i . ?
., ,7,
,!.,.., .,,? ,
 i . 
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@Mt
USN
17EC34
Third Semester B.E. Degree Examination, Dec.2019/Jin.2020
Digital Electronics
Time: 3 hrs. Max. Marks: 100
Note: Answer any FIVE full questions, choosing ONE full question from each module.
U
s
P Module1
? 1 a. Express the following functions into a canonical form:
,.,
0 f
i
= a + be + bcd
ii) f2 = a(b + c) (b + c + d)
_
?
,,
(08 Marks)
t.11
cz b. Represent the number of days in a month for a nonleap year by a truth cable, indicating the
c.=
output of a invalid inputs if any by '0'. (06 Marks)
dijor j;
?
6
.
S3 c. Simplify the given function using Kmap method
ta 0
c oc,
f(abcd) = Ern (1, 2, 4, 11, 13, 14, 15) +d (0, 5, 7, 8, 10).
*E +
(06 Marks)
. cs,
c *C 71
E d)
L.. .
OR
,i, c
.c o
2 a. Find all prime implicants of the function using Quineindustry method and verify the same
=
by Kmap method .f(abcd) = Em (0, 2, 3, 4, 8, 10, 12, 13, 14) (10 Marks)
ai ti
,
c
. a
0 b.
Find minimal sum and minimal product for the incomplete Boolean function using Kmap

2
.7...
1:1 5
f(abcd) = Em(6, 7, 9, 10, 13) + d E(1, 4, 5, 11, 15). (10 Marks)
cr
U 4.)
7 O
:
CZ
0
c     
Module2
0
C
ct
3 a. Design two bit magnitude comparator. (10 Marks)
. ,
74 b. Design 4:2 priority encoder with a valid output where highest priority is given to the highest
45 73
bit position. (10 Marks)
il
0
O ,.
a B.
OR
0 F,
, ,
d
4 a. Design and realize the Boolean function using IC74139.
6 .2 fl(ab) = E(0, 2), f2(abc) = E(1, 3, 5, 7). (05 Marks)
a.) 'F v ;
b. Explain how look ahead carry adder circuit will reduce the propagation delay with the help
.
,
..
0
.
c 
c t.
of carry propagate and carry generate function. (08 Marks)
L Q.)
E
1
/
> , c ? 
C. Implement the Boolean function f(abcd) = E(0, 2, 4, 5, 7, 9, 10, 14) using multiplexers with
0
? to two 4:1 MUX with variable 'a' and 'b' are connected to their select lines in first level and
E.
c
t 
one 2:1 MUX with variable 'c' connected to its select line in second level. (07 Marks)
c'
3
E
0
. >,
6
.,
Module3
_4 csi
5 a. With the help of logic circuit and waveforms. Explain switch bouncing applications using
? ?
0
0,
SR latch. (06 Marks)
z
b.
Write the characteristics equation for SR, JK flip flop. (06 Marks)
,:. c.
With neat logic diagram, and waveform. Explain the operation of masterslave JK flipflop.
?_
,,,.,?
...., . ...
(08 Marks)
;,. ... . ..
1 of 2 ..'
/N .
'
/ ... /
,i . ?
., ,7,
,!.,.., .,,? ,
 i . 
c I k
OR
6 a. List the difference between combinational and sequentional circuit. (06 Mari .
b. Explain the operation of clocked SR flipflop using NANDgate. s (06 Marks; ,
c. What is the significance of Edge triggering? Explain the working of positive edge triggered
D flipflop with their function table. (08 Marks)
Module4
7 a. With neat diagram, explain the operation of universal shift register. (08 Marks)
b. Design 3 bit binary synchronous down counter using JK Flip Flop. Write excition table,
transition table, and logic diagram. (12 Marks)
OR
8 a. What is register? With heat circuit diagram, explain the operation of 4bit ring counter.
(07 Marks)
b. With logic diagram, sequence table, decoding logic. Explain the operation of mod7 twisted
ring counter. (07 Marks)
c. Explain the working of 4 bit binary ripple counter using positive edge triggered Tflipflop
also draw timing diagram, truth table. (06 Marks)
Module5
9 a. Write the difference between Moore and Mealy model with necessary block diagram.
(08 Marks)
b.
Design asynchronous circuit using positive edge triggered JK flipflop with minimal
combinational gating to generate the following sequence. 0120: if input X = 0 and
0 ? 2 ? 1? 0; if input X = 1, provide an output which goes high to indicate the nonzero state
in the 0120 sequence. Is this a mealy machine? (12 Marks)
OR
10 a. Design a cyclic mod8 synchronous binary counter using JK flipflop.
b. Analyze the given sequential circuit show in Fig.Q.10(b) and obtain.
i) Flipflop Input and Output Equation
ii) Transition Equation
iii) Transition Table (N)
iv) State Table
v) State Diagram.
(10 Marks)
(10 Marks)
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This post was last modified on 28 February 2020