Download JNTUK B-Tech 2020 R19 CSE B19 CS 1202 Digital Logic Design Model Question Paper

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I B. Tech II Semester (R19) Regular Examinations

DIGITAL LOGIC DESIGN

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(Common to CSE & IT)

MODEL QUESTION PAPER

TIME: 3 Hrs. Max. Marks: 75 M

Answer ONE Question from EACH UNIT

All questions carry equal marks

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UNIT -1

1. a).
   1. Convert (1032.2)4 to decimal. Cl| K2 8
   2. Perform the subtraction using 2’s complement 100-110000
   b). Reduce the Boolean Functions to minimum number of literals Cl| K2 7
   1. (1) ABC+A'B'C+A'BC+ABC' +A'B'C' to five literals
   2. (ii) (A+C+D)(A+C+D')(A+C'+D)(A+B') to five literals

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OR

1. a). Convert the function to another canonical form. F(x,y,z)=n(0,3,6,7) Cl | K2 8
   b). Implement the Boolean function F=xy+x'y'+y'z with Cl| K2 7
   1. AND ,OR and NOT gates
   2. OR,NOT gates

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   3. AND, NOT gates

UNIT - II

1. a). Simplify the Boolean Function using K-Map. C2| K3 8
   F(A,B,C,D)=ACE+A'CD'E+A'C'DE
   

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   D(A,B,C,D)=DE'+A'D'E+AD'E'
   b). Design and explain Binary Adder/ Subtractor. C2 | K3 7

OR

1. a). Simplify the Boolean Function to-product of sums. F(A,B,C,D)=n(0,1,2,3,4,10,11) | C2 | K2 8
   b). Design and explain Decimal Adder. C2 | K2 7

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UNIT - III

1. a). Design and explain abt JK Flip flop. C3 | K3 8
   b). Explain abt State Reduction and Assignment with example. C3 | K3 7

OR

1. Explain abt design procedure of sequential circuits with an example C3| K4 | 15

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UNIT - IV

1. a). Design and explain abt Shift Register. C4 | K3 8
   b). Design and explain abt BCD Ripple counter . C4 | K3 7

OR

1. a). Design and explain abt Universal Shift Register. C4 | K3 8
   

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   b). Design and explain abt Synchronous Binary counter. C4 | K3 7

UNIT - V

1. a). Explain abt Memory decoding of RAM. C5 | K3 8
   b). Explain abt ROM Variants C5| K3 | 7

OR

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1. a). Explain PLA and PAL C5| K3 | 8
   b). Explain abt Hamming code with an example C5| K3 7

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