Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 5th Semester (Fifth Semester) 2017-2018 NEC501 Integrated Circuits Question Paper
Paper Id:3049 R0" N??
B TECH
(SEM 5) THEORY EXAMINATION 2017-18
INTEGRATED CIRCUITS
Time: 3 Hours T otal Marks: 100
Notes:
Note :- All sections are c0mpuls0ry.lf require any missing data; then choose suitably.
SECTION ? A
1 This question consist of short answer questions. Attempt all parts of this question. All parts carry equal
marks.
2 X 10 = 20
a) If the open loop gain of an operational ampli?er is very large. Does the closed loop gain
depend upon the external components or the operational amplifier justify
b) What is meant by the term matched transistors.
0) Define and give significance of Slew Rate.
d) What is a Super Diode.
6) Give two application of analog multiplier.
f) What do you mean by a frequency response of a filter circuit.
g) Differentiate between Comparator and Schmitt trigger.
h) Describe the need of voltage limiter circuits.
i) The basic step of a 8-bit DAC is 20mV. If 00000000 represents 0V, what is represented by the
input 10110111.
j) What do you mean by a CMOS circuit logic.
SECTION ? B
2 Attempt any Three parts of this question. A11 paits carry equal marks. 10 X 3: 30
(a) What are the desirable characteristics of current mirror circuits. Explain the circuit of Wilson MOS
current mirror. Also discuss how it can be improved.
(b) Derive the expression of voltage gain in KHN Biquad Filter. Draw the KHN Biquad ?lter and drive
transfer function of the EFF and LPF from that.
(0) Discuss the features of CMOS circuit. Realize one AND-OR-INVERT (A01) and one OR- AND?
INVERT (OAI) function using CMOS logic circuit.
(d) What do you mean by the quadrant operation of multiplier. Draw and explain a GILBERT analog
multiplier.
(e) Draw the block diagram of a PLL and explain its operation. Explain lock?in?range, capture range
and pull-in time of a PLL. List the application of PLL.
SECTION ? C
Attempt any Two parts of each questions of this section. All question carry equal marks
10 X 5 = 50
a) Describe the operation and characteristics of a BJT complementary push-pull output stage.
b) Determine the small-signal model of the second stage of the 741 op-amp.
c) The parameter of the three transistor CM are VCC = 9V, VEE = 0, R1=12KQ, VBE(0n) = 0.7V,
B = 75, VA = 00. Calculate the value Of current, Irefa IO,IC1, 1131, 1132 ,1133 ,IE3.
a) Draw the generalized impedance conveiter and derive its impedance equation. Also simulate an
Inductor.
b) Derive the output expression for RC Phase Shift Oscillator.
0) Compare and contrast active filters and passive ?lters. Design a second order low pass
Butterworth filter to have cut-off frequency of lKHZ.
a) Give CMOS implementation of 21 SR ?ip??op and explain its working.
b) Give two different CMOS realization of the Exclusive ? OR gate function in which the PDN and
FUN are dual networks.
0) Discuss D?F/F circuit using NAND CMOS gates.
a) Draw & explain the circuit of triangular wave generator. How square wave can be obtained
using this triangle wave.
b) Describe temperature compensated Log amplifier using two op-amp & explain its operation.
0) Explain how a Schmitt Trigger circuit works with a neat diagram. Design an Schmitt trigger with
VUT = 2V , VLT = -1V. Assume i V52?: i 13V.
a) Draw and Explain the block diagram of 1C 555.
b) Explain the operation of dual slope ADC.
0) Design a 555 timer as astable multivibrator giving its block diagram which provide an output signal
frequency of 2 KHz and 75 % duty cycle.
This post was last modified on 29 January 2020