JNTU-KAKINADA : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).

JNTU-KAKINADA : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).



II Year – I Semester



1Managerial Economics and Financial Analysis4+1* 4
2Probability & Statistics4+1* 4
3Mathematical Foundations of Computer  Science and Engineering4+1* 4
4Digital Logic Design4+1* 4
5Electronic Devices and Circuits4+1* 4
6Data Structures4+1* 4
7Electronic Devices and Circuits Lab32
8Data Structures Lab32
9Professional Communicational skills21
Total Credits29




II Year B.Tech. – I Semester


Unit  I : Number Systems

Binary, Octal, Decimal, Hexadecimal Number Systems. Conversion of Numbers From One Radix To Another Radix , r’s Complement and (r-1)’s Complement Subtraction of Unsigned Numbers, Problems, Signed Binary Numbers, Weighted and Non weighted codes

Unit II:Logic Gates And Boolean Algebra

Basic Gates NOT, AND, OR, Boolean Theorms,Complement And Dual of Logical Expressions, Universal Gates, Ex-Or and Ex-Nor Gates, SOP,POS, Minimizations of Logic Functions Using Boolean Theorems, Two level Realization of Logic Functions Using Universal Gates.  Verilog programming for the minimized logic functions.

Unit III: Gate- Level Minimization

Karnaugh Map Method(K-Map): Minimization of Boolean Functions maximum upto  Four Variables , POS And SOP, Simplifications With Don’t Care Conditions Using K-Map.

Unit IV: Combinational Arithmetic Logic Circuits

Design of Half Adder, Full Adder, Half Subtractor ,  Full Subtractor, Ripple Adders and Subtractors, Ripple Adder/Subtractor Using Ones and Twos Complement Method. Serial Adder , Carry Look Ahead Adder.

Unit V: Combinational Logic Circuits

Design of Decoders, Encoders, Multiplexers, Demultiplexers, Higher Order Demultiplexers and Multiplexers, Realization of Boolean Functions Using Decoders and Multiplexers, Priority Encoder, Code Converters, Magnitude Comparator.

Unit VI:  Introduction to Programmable Logic Devices (PLOs)

PLA, PAL, PROM. Realization of Switching Functions Using PROM, PAL and PLA. Comparison of PLA, PAL and PROM..

Unit VII: Introduction to Sequential Logic Circuits

Classification of Sequential Circuits, Basic Sequential Logic Circuits: Latch and Flip-Flop, RS- Latch Using NAND and NOR Gates, Truth Tables. RS,JK,T and D Flip Flops , Truth and Excitation Tables, Conversion of Flip Flops. Flip Flops With Asynchronous Inputs (Preset and Clear).

Unit VIII: Registers and Counters

Design of Registers, Buffer Register, Control Buffer Registers, Bidirectional Shift Registers, Universal Shift Register, Design of Ripple Counters, Synchronous Counters and Variable Modulus Counters, Ring Counter, Johnson Counter.


1. Digital Design ,4/e, M.Morris Mano, Michael D  Ciletti, PEA

2. Fundamentals of Logic Design, 5/e, Roth, Cengage


1. Switching and Finite Automata Theory,3/e,Kohavi, Jha, Cambridge.

2. Digital Logic Design, Leach, Malvino, Saha,TMH

3.Modern Digital Electronics, R.P. Jain, TMH


II Year B.Tech. – I Semester



Electron Ballistics and Applications: Force on Charged Particles in Electric field, Constant Electric Field, Potential, Relationship between Field Intensity and Potential, Two Dimensional Motion, Electrostatic Deflection in Cathode ray Tube, CRO, Force in Magnetic Field, Motion in Magnetic Field, Magnetic Deflection in CRT, Magnetic Focusing, Parallel Electric and Magnetic fields and Perpendicular Electric and Magnetic Fields.

Unit- II

Review of Semi Conductor Physics : Insulators, Semi conductors, and Metals classification using Energy Band Diagrams, Mobility and Conductivity, Electrons and holes in Intrinsic Semi conductors, Extrinsic Semi Conductor, (P and N Type semiconductor) Hall effect, Generation and Recombination of Charges, Diffusion, Continuity Equation, Injected Minority Carriers, Law of Junction, Fermi Dirac Function, Fermi level in Intrinsic and Extrinsic Semiconductor

Unit- III

Junction Diode Characteristics  : Open circuited P N Junction, Forward and Reverse Bias, Current components in PN Diode, Diode Equation,Volt-Amper Characteristic, Temperature Dependence on V – I characteristic, Step Graded Junction, Diffusion Capacitance and Diode Resistance (Static and Dynamic), Energy Band Diagram of PN Diode,

Special Diodes: Avalanche and Zener Break Down, Zener Characterisitics,  Tunnel Diode, Characteristics with the help of Energy Band Diagrams, Varactor Diode, LED, PIN Diode,  Photo Diode

Unit IV

Rectifiers and Filters: Half wave rectifier, ripple factor, full wave rectifier(with and without transformer), Harmonic components in a rectifier circuit, Inductor filter, Capacitor filter, L- section filter, P- section filter, Multiple L- section and Multiple  P section filter, and comparison of various filter circuits  in  terms of ripple factors, Simple circuit of a regulator using zener diode, Series and Shunt voltage regulators

Unit- V

Transistors :

Junction transistor, Transistor current components, Transistor as an amplifier, Characteristics of Transistor in Common Base and  Common Emitter Configurations, Analytical expressions for Transistor Characteristics, Punch Through/  Reach Through, Photo Transistor, Typical transistor junction voltage values.

Unit VI

Field Effect Transistors:

JFET characteristics (Qualitative and Quantitative discussion), Small signal model of JFET, MOSFET characteristics (Enhancement and depletion mode), Symbols of MOSFET, Introduction to SCR and UJT and their characteristics,


Transistor Biasing and Thermal Stabilization : Transistor Biasing and Thermal Stabilization: Operating point, Basic Stability, Collector to Base Bias, Self Bias Amplifiers, Stabilization against variations in VBE,, and ? for the self bias circuit, Stabilization factors, (S, S, S‘’), Bias Compensation,  Thermistor and Sensitor compensation,   Compensation against variation in VBE, Ico,,  Thermal runaway, Thermal stability


Small signal low frequency Transistor models: Two port devices and the Hybrid model, Transistor Hybrid model, Determination of h-parameters from characteristics, Measurement of h-parameters, Conversion formulas for the parameters of three transistor configurations, Analysis of a Transistor Amplifier circuit using h- parameters, Comparison of Transistor Amplifier configurations

Text Books

1.  Electronic Devices and Circuits – J. Millman,  C.C. Halkias,  Tata Mc-Graw Hill


1.  Electronic Devices and Circuits – K Satya Prasad,  VGS Book Links

2.  Integrated Electronics – Jacob Millman,  Chritos C. Halkies,, Tata Mc-Graw Hill, 2009

3. Electronic Devices and Circuits – Salivahanan, Kumar, Vallavaraj, TATA McGraw Hill, Second Edition

4. Electronic Devices and Circuits – R.L. Boylestad and Louis Nashelsky, Pearson/Prentice Hall,9thEdition,2006

5. Electronic Devices and Circuits -BV Rao, KBR Murty, K Raja Rajeswari, PCR Pantulu, Pearson, 2nd edition



II Year B.Tech. – I Semester


UNIT I: Recursion and Linear Search:

Preliminaries of algorithm,  Algorithm analysis and complexity.

Recursion: Definition, Design Methodology and Implementation of recursive algorithms, Linear and binary recursion, recursive algorithms for factorial function, GCD computation, Fibonacci sequence, Towers of Hanoi, Tail recursion

List Searches using Linear Search, Binary Search, Fibonacci Search,

UNIT II: Sorting Techniques:

Basic concepts, Sorting by : insertion (Insertion sort), selection (heap sort), exchange (bubble sort, quick sort), distribution (radix sort ) and merging  (merge sort )  Algorithms.

UNIT III: Stacks and Queues:

Basic Stack Operations, Representation of a Stack using Arrays, Stack Applications: Reversing list,   Factorial Calculation, In-fix- to postfix Transformation, Evaluating Arithmetic Expressions.

Queues: Basic Queues Operations, Representation  of a  Queue using array, Implementation of Queue Operations using Stack,  Applications of Queues-Round robin Algorithm, Enqueue,  Dequeue, Circular Queues,   Priority Queues.

UNIT IV:  Linked Lists:

Introduction, single linked list, representation of a linked list in memory, Operations on a single linked list, merging two single linked lists into one list, Reversing a   single  linked list, applications of single linked list to represent polynomial expressions and sparse matrix manipulation, Advantages and disadvantages of single  linked list, Circular linked list,  Double linked list

UNIT V: Trees:

Basic tree concepts, Binary Trees: Properties, Representation of Binary Trees using arrays and linked lists, operations on a Binary tree , Binary Tree Traversals (recursive), Creation of binary tree from in-order and pre(post)order traversals,

UNIT VI: Advanced concepts of Trees:

Tree Travels using stack (non recursive), Threaded Binary Trees. Binary search tree, Basic concepts, BST operations: insertion, deletion,

Balanced binary trees – need, basics and applications in computer science (No operations )

UNIT VII: Graphs:

Basic concepts, Representations of Graphs: using Linked list and adjacency matrix, Graph algorithms

Graph Traversals (BFS & DFS), applications: Dijkstra’s shortest path, Transitive closure, Minimum Spanning Tree using     Prim’s Algorithm, warshall’s Algorithm.

Unit VIII: Sets:

Definition, Representation of Sets using Linked list, operations of sets using linked lists, application of sets- Information storage using bit strings

Abstract Data Type Introduction to abstraction, Model for an Abstract Data Type, ADT Operations, ADT Data Structure, ADT Implementation of stack and queue .


1.      Data Structures, 2/e, Richard F, Gilberg , Forouzan, Cengage

2.      Data Structures and Algorithms, 2008,G.A.V.Pai, TMH


1.      Data Structure with C, Seymour Lipschutz, TMH

2.      Classic Data Structures, 2/e, Debasis ,Samanta,PHI,2009

3.      Fundamentals of Data Structure in C, 2/e, Horowitz,Sahni, Anderson Freed,University Prees


II Year B.Tech. – I Semester


PART A : (Only for viva voce Examination)


1. Identification, Specifications, Testing of R, L, C Components (Colour Codes), Potentiometers, Switches (SPDT, DPDT, and DIP), Coils, Gang Condensers, Relays, Bread Boards.

2. Identification, Specifications and Testing of Active Devices, Diodes, BJTs, Lowpower JFETs, MOSFETs, Power Transistors, LEDs, LCDs, Optoelectronic Devices, SCR, UJT, DIACs, TRIACs, Linear and Digital ICs.

3. Soldering practice – Simple Circuits using active and passive components.

4. Single layer and Multi layer PCBs (Identification and Utility).

5. Study and operation of

• Multimeters (Analog and Digital)

• Function Generator

• Regulated Power Supplies

  1. Study and Operation of CRO.

PART B : (For Laboratory examination – Minimum of 10 experiments)

1.  Frequency measurment using Lissajous Figures

2. PN Junction diode characteristics   A. Forward bias  B. Reverse bias.( cut-in voltage & Resistance calculations)

3. Zener diode characteristics and Zener as a regulator

4. Transistor CB characteristics (Input and Output) & h Parameter calculations

5. Transistor CE characteristics (Input and Output) & h Parameter calculations

6. Rectifier without filters (Full wave & Half wave)

7. Rectifier with filters (Full wave & Half wave)

8. FET characteristics

9. SCR Charecteristics

10. UJT Charectristics

11. CE Amplifier

12. CC Amplifier (Emitter Follower).


Equipment required for Laboratories:

  1. Regulated Power supplies (RPS)                        -           0-30v
  2. CROs                                                              -           0-20M Hz.
  3. Function Generators                                         -           0-1 M Hz.
  4. Multimeters
  5. Decade Resitance Boxes/Rheostats
  6. Decade Capacitance Boxes
  7. Micro Ammeters (Analog or Digital)                 -           0-20 µA, 0-50µA, 0-100µA, 0-                                                                                              200µA
  8. Voltmeters (Analog or Digital)                         -           0-50V, 0-100V, 0-250V
  9. Electronic Components                                   -          Resistors, Capacitors, BJTs, LCDs,                                                                                        SCRs,  UJTs, FETs, LEDs,



Click on the below link to Download the Official Notification :

JNTU-KKD : Revised Course Structure and Syllabus-B.Tech (CSE and IT)-II YEAR-I Semester (R10 Students).

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  1. balu August 6, 2011 Reply

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