Download VTU BE 2020 Jan CSE Question Paper 15 Scheme 7th Sem 15CS72 Advanced Computer Architecture

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Seventh Semester B.E. Degree Examination, DecilitIaaii.2020
Advanced Computer Architecture
Time: 3 hrs. Max. Marks: 80
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Note: Answer any FIVE full questions, choosing ONE full question from each module.

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Module-1
a. With a neat diagram explain the elements of modern computer system. (08 Marks)
b. Explain Flynn's classification of computer architecture. (08 Marks)
OR
2 a. Define data dependency. Explain different functions of data dependency with the help of

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dependency graph. (08 Marks)
b. A 4 MHz processor was used to execute a benchmark program with the following
instruction mix and clock cycle counts.
Instruction type Instruction count Cycles/instruction
Integer arithmetic 45000 1

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Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2
Determine the effective CPI, MIPS rate and execution time for this program. (08 Marks)
Module-2

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3 a. Explain the architecture of VLIW processor and its pipeline operations. (08 Marks)
b. Explain the inclusion property and locality of reference along with its types in multilevel
memory hierarchy. (08 Marks)
OR
4 a. Explain page replacement policies with the help of an example. (08 Marks)

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b. Give the characteristics of symbolic processors. (08 Marks)
Module-3
5 a. Explain bus arbitration and its types in multiprocessor systems. (08 Marks)
b. Explain any two mapping techniques. (08 Marks)
OR

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6 a. Explain the following terms associated with cache and memory architecture:
(i) Low order memory interleaving
(ii) Atomic v/s non-atomic memory
(iii) Physical address cache vs virtual address cache
(iv) Memory bandwidth and fault tolerance. (08 Marks)

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Seventh Semester B.E. Degree Examination, DecilitIaaii.2020
Advanced Computer Architecture

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Time: 3 hrs. Max. Marks: 80
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Note: Answer any FIVE full questions, choosing ONE full question from each module.
Module-1
a. With a neat diagram explain the elements of modern computer system. (08 Marks)
b. Explain Flynn's classification of computer architecture. (08 Marks)

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OR
2 a. Define data dependency. Explain different functions of data dependency with the help of
dependency graph. (08 Marks)
b. A 4 MHz processor was used to execute a benchmark program with the following
instruction mix and clock cycle counts.

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Instruction type Instruction count Cycles/instruction
Integer arithmetic 45000 1
Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2

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Determine the effective CPI, MIPS rate and execution time for this program. (08 Marks)
Module-2
3 a. Explain the architecture of VLIW processor and its pipeline operations. (08 Marks)
b. Explain the inclusion property and locality of reference along with its types in multilevel
memory hierarchy. (08 Marks)

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OR
4 a. Explain page replacement policies with the help of an example. (08 Marks)
b. Give the characteristics of symbolic processors. (08 Marks)
Module-3
5 a. Explain bus arbitration and its types in multiprocessor systems. (08 Marks)

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b. Explain any two mapping techniques. (08 Marks)
OR
6 a. Explain the following terms associated with cache and memory architecture:
(i) Low order memory interleaving
(ii) Atomic v/s non-atomic memory

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(iii) Physical address cache vs virtual address cache
(iv) Memory bandwidth and fault tolerance. (08 Marks)
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b. Consider the following pipelined processor within 3 stages this pipeline has total evaluation
time of 8 clock cycles. All successor st ges must be used after each clock cycle.

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0 1 2 3 4 5 6 7 8
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S3 X
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(i) List the set of forbidden latencies between task initiations

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(ii) Draw the state diagram which shows all possible latency cycles
(iii) List all greedy cycles
(iv) Value of MAL.
Module-4
7 a. Explain hierarchical bus system with neat diagram.

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b. Explain crossbar networks along with its advantages and limitations.
OR
8 a. Explain snoopy protocols with its approaches.
b Briefly explain message routing schemes.
Module-5

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9 a. Define parallel programming model. Explain any two models.
b. Mention branch prediction methods and explain.
OR
10 a.
With the help of a neat diagram explain compilation phases in code generator.

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b. Explain different language features for parallelism.
(08 Marks)
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(08 Marks)
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(08 Marks)

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