Download PTU M.Tech. ECE 2nd Semester 74282 VLSI DESIGN Question Paper

Download PTU. I.K. Gujral Punjab Technical University (IKGPTU) M.Tech. ECE 2nd Semester 74282 VLSI DESIGN Question Paper.

1 | M-74282 (S9)-1740

Roll No. Total No. of Pages : 02
Total No. of Questions : 08
M.Tech.(ECE) (2016 Batch) EL-I (Sem.?2)
VLSI DESIGN
Subject Code : MTEC-204B
M.Code : 74282
Time : 3 Hrs. Max. Marks : 100

INSTRUCTIONS TO CANDIDATES :
1. Attempt any FIVE questions out of EIGHT questions.
2. Each question carries TWENTY marks.

1. (a) Design a Mod-6 counter using SR flip-flop and also convert it into counter using JK
flip- flop. (14)
(b) What are the various types of ROM?s? Discuss their relative advantages and
disadvantages. (6)
2. (a) Explain memory structure of SRAM with read and write circuitry with the help of
read and write timing diagrams. (10)
(b) Give a brief note on the looping statements available in Verilog HDL. (10)
3. A sequential network has one input(X) and two outputs (Z
1
and Z
2
). An output
Z
1
=1 occurs every time the input sequence 010 is completed provided that the sequence
100 has never occurred. An output Z
2
= 1 occurs every, time the input sequence 100 is
completed. Note that once a Z
2
= 1 output has occurred, Z
1
= 1 can never occur, but not
vice-versa. Derive a Mealy state graph and table with a minimum number of states. Also
realize the network using JK flip-flops and NAND gates. (20)
4. (a) Write a Verilog code for 4-bit binary to gray code converter using if-else statement.
(10)
(b) Design a full-adder using : (10)
i) Only NAND gates
ii) Only NOR gates
5. (a) What is meta-stability in digital circuits? Discuss methods to eliminate it. (10)
(b) Explain leakage currents and refresh operation in DRAM cells. (10)
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1 | M-74282 (S9)-1740

Roll No. Total No. of Pages : 02
Total No. of Questions : 08
M.Tech.(ECE) (2016 Batch) EL-I (Sem.?2)
VLSI DESIGN
Subject Code : MTEC-204B
M.Code : 74282
Time : 3 Hrs. Max. Marks : 100

INSTRUCTIONS TO CANDIDATES :
1. Attempt any FIVE questions out of EIGHT questions.
2. Each question carries TWENTY marks.

1. (a) Design a Mod-6 counter using SR flip-flop and also convert it into counter using JK
flip- flop. (14)
(b) What are the various types of ROM?s? Discuss their relative advantages and
disadvantages. (6)
2. (a) Explain memory structure of SRAM with read and write circuitry with the help of
read and write timing diagrams. (10)
(b) Give a brief note on the looping statements available in Verilog HDL. (10)
3. A sequential network has one input(X) and two outputs (Z
1
and Z
2
). An output
Z
1
=1 occurs every time the input sequence 010 is completed provided that the sequence
100 has never occurred. An output Z
2
= 1 occurs every, time the input sequence 100 is
completed. Note that once a Z
2
= 1 output has occurred, Z
1
= 1 can never occur, but not
vice-versa. Derive a Mealy state graph and table with a minimum number of states. Also
realize the network using JK flip-flops and NAND gates. (20)
4. (a) Write a Verilog code for 4-bit binary to gray code converter using if-else statement.
(10)
(b) Design a full-adder using : (10)
i) Only NAND gates
ii) Only NOR gates
5. (a) What is meta-stability in digital circuits? Discuss methods to eliminate it. (10)
(b) Explain leakage currents and refresh operation in DRAM cells. (10)
2 | M-74282 (S9)-1740

6. (a) List the various scalar data types and explain them with the help of examples. (10)
(b) Write a VHDL code for 4-bit Binary to Gray code converter using behavioral style of
modeling. (10)
7. (a) Explain the structural difference between a ROM and a PLA and implement the
following function using ROM and PLA design :
F (A, B, C, D) = ? (0, 1, 3, 6, 8, 9, 10, 12, 15). (14)
(b) Discuss the role of CLBs in FPGAs. (6)
8. (a) Differentiate between sequential and concurrent circuits by giving an appropriate
example. (10)
(b) Write a short note on : (10)
i) CPLD
ii) PLA










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