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Total No. of Pages : 01
Total No. of Questions : 08
M.Tech (CSE Engg.) Big Data (Campus) (Sem.-2)
ADVANCED COMPUTER ARCHITECTURE
Subject Code : CSB-205
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M.Code: 51089
Time: 3 Hrs.
Max. Marks : 50
INSTRUCTIONS TO CANDIDATES :
- Attempt any FIVE questions out of EIGHT questions.
- Each question carries TEN marks.
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- Explain the description of control sequence for simple RISC computer.
- Write a short note on hardwired control unit design.
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- What is cache coherence problem? Discuss its protocols.
- List the levels of cache in computer architecture? Discuss performance issues in memory.
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- Differentiate between homogeneous and heterogeneous cores in architecture.
- Discuss the optimal resource sharing strategies in multi core architecture.
- Why is it required for a computer to do parallel computing? Write the reasons for its failure?
- Define :
- Concurrency and Parallelism
- Load Balancing
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- What are the design challenges in Multithreading concepts?
- How Intel Corporation is supporting multithreading capabilities using Intel compilers?
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- Explain the various factors on which performance of processors is measured.
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- How OpenMP is used for parallelism within a multi-core programming?
- Give an overview of Extensive API Library for finer control.
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NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any page of Answer Sheet will lead to UMC against the Student.
1| M-51089
(S35)-307
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This download link is referred from the post: PTU M.Tech 2nd Semester Last 10 Years 2010-2020 Previous Question Papers|| Punjab Technical University
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