Download GTU BE/B.Tech 2019 Winter 3rd Sem New 3130306 Fundamentals Of Digital Electronics Question Paper

Enrolment No.

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Subject Code: 3130306

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BE - SEMESTER- III (New) EXAMINATION — WINTER 2019

Subject Name: Fundamentals of Digital Electronics

Time: 02:30 PM TO 05:00 PM

Instructions:

1. Attempt all questions.

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2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

1. (a) Subtract the following binary numbers by the 2's and 1's complement method.
   10110-1011 Marks 03
2. (b) Encode data bits 1011 into the 7-bit even parity Hamming code. Find and correct error from 7-bit hamming code given below.
   

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   1110110 Marks 04
3. (c) Explain TTL and CMOS realization of AND and OR gate. Marks 07

1. (a) For a two input AND & OR gate, Determine its output waveform in relations to input waveform A & B. Input A has frequency 2Hz with duty cycle 50% and Input B has frequency 1Hz with duty cycle 70%. Marks 03
2. (b) Explain EX-OR and EX-NOR gate using its truth table, Symbol, and logic diagram. Marks 04
3. (c) Reduce the expression =), m(1,4,7,10,13) + d(5,14,15) using k-map and implement the minimal expression in universal logic. Marks 07

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OR

1. (a) Find the minimal expression for f = [[ M(2,8,9,10,11,12,14) using tabular method. Marks 07
2. (b) Reduce the Boolean Expression: f = AB + AC + ABC(AB + C). Marks 03
3. (c) Design 4-input priority encoder. Marks 04

1. (a) Design Half adder and Half subtractor using universal logic. Marks 07

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OR

1. (a) Draw logic diagram of 3-8 line decoder: Marks 03
2. (b) Find out Minterms and Maxterms for-Boolean expression: f=A(A+B)(A+B + (). Marks 04
3. (c) Implement the logic function F=),m(0,1,2,3,4,10,11,14,15) using a 16:1 MUX and 8:1 MUX. Marks 07

1. (a) Explain 1-bit Magnitude comparator with logic diagram. Marks 03

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2. (b) Design full adder using PAL circuit. Marks 04
3. (c) Design a 4-bit Binary to Gray Code converter with logic diagram. Marks 07

OR

1. (a) Write comparison of programmable logic devices. Marks 03
2. (b) Design full subtractor using PLA circuit. Marks 04

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3. (c) Explain design of a synchronous 3-bit Up-Down counter using J-K flip-flops. Marks 07

1. (a) Write comparison between synchronous and asynchronous sequential circuits. Marks 03
2. (b) Describe master-slave pulse triggered D-flip-flop. Marks 04
3. (c) Explain edge-triggered J-K flip-flop and T-flip-flop. Marks 07

OR

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1. (a) Write excitation tables of S-R, J-K, D, and T flip-flop. Marks 03
2. (b) Describe Serial In, Parallel Out shift register. Marks 04
3. (c) Design and explain Asynchronous two bit ripple up and down counter using negative edge triggered J-K flip-flops. Marks 07

Date: 3/12/2019

Total Marks: 70

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