GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER-1V (NEW) EXAMINATION - WINTER 2018
--- Content provided by FirstRanker.com ---
Subject Code:2140910 Date:28/11/2018Subject Name:Digital Electronics
Time: 02:30 PM TO 05:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
--- Content provided by FirstRanker.com ---
2. Make suitable assumptions wherever necessary.3. Figures to the right indicate full marks.
MARKS
Q.1 (a) Convert (0.6875)10 to binary equivalent number 03
(b) Using 10’s complement ,subtract (i) (72532-3250)10 04
--- Content provided by FirstRanker.com ---
(11) (3250-72532)10(¢) State and Prove De-Morgan’s theorems with necessary truth table. 07
Q.2 (a) Prove that a positive-logic AND gate is a negative-logic OR gate. 03
(b) Why NAND gate and NOR gate are known as universal gates? 04
Obtain Ex-OR and Ex-NOR using NAND.
--- Content provided by FirstRanker.com ---
(¢) Write short note on error detection codes. 07OR
(¢) Write short note on Gray code. 07
Q.3 (a) Reduce the expression f= (B+BC) (B+BC)(B+D) 03
(b) Define the following general characteristics of logic families. (1) 04
--- Content provided by FirstRanker.com ---
Propagation delay time (ii) Noise Margin (iii) Fan — out(iv) Power dissipation
(¢) Minimize the following Boolean expression using K- Map and 07
realize it using logic gates.
F(A,B,C.D)=)m(0,1,5,9,13,14;15)+d(3.4,7,10,11)
--- Content provided by FirstRanker.com ---
OR
Q.3 (a) Compare K-map and tabular method of minimization. 03
(b) Compare Counters and Registers. 04
(¢) Express the Boolean function F=A +AC in a sum of min-terms. 07
Q.4 (a) Distinguish between combinational and sequential logic circuits. 03
--- Content provided by FirstRanker.com ---
(b) Explain full-subtractor in brief. 04(¢) Write short'note on Multiplexers. 07
OR
Q.4 (a) State the basic difference between synchronous and asynchronous 03
counters.
--- Content provided by FirstRanker.com ---
(b) Explain operation of 4 bit left shift register with necessary diagrams. 04(¢) Differentiate between level triggering and edge triggering of flip- 07
flops. Explain Master-Slave J-K flip-flop configuration.
Q.5 (a) Define following specification of ADC (i) Resolution (ii) Conversion 03
time (ii1) Quantization error
--- Content provided by FirstRanker.com ---
(b) Compare between various types of ROM. 04(¢) Explain internal organization of RAM , Draw and explain with 07
necessary block diagram the process of writing in memory and
reading from memory also.
OR
--- Content provided by FirstRanker.com ---
Q.5 (a) Define following specification of DAC (i) Resolution (ii) Settling 03
time (iii) Settling time (iv) Monotonicity.
(b) Compare various D/A Converters. 04
(¢) Describe operation of D/A converter with binary weighted resistors. 07
--- Content provided by FirstRanker.com ---
This download link is referred from the post: GTU BE/B.Tech 2018 Winter Question Papers || Gujarat Technological University
--- Content provided by FirstRanker.com ---