Download JNTUA MCA 2018 July Reg-Supply 2nd Sem 17F00202 Computer Organization Question Paper

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Code: 17F00202

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Answer all the questions

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1. (a) What is meant by decoder? Explain 3 — to — 8 line decoder with diagram and truth table.
   OR
   (b) Design a combination circuit for a full subtractor and explain it in detail.
2. (a) Explain the read and write operations with respect to the association memory. Discuss RAM and ROM chips with diagrams.
   OR
   

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   (b) List out the factors that determine the storage device performance in main memory and 128 blocks in cache with 16 blocks per cache.
3. Which data structures can be the best supported using:
   (i) Indirect addressing mode.
   (ii) Auto increment/auto decrement addressing mode.
   Explain one-address, 2-address and 3-address instructions related to CPU organizations.
   

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   OR
   Write an ALP using 8086 instructions to generate and add the first 10 even numbers and save the numbers and result in memory location num and sum.
4. Compare I/O versus memory bus.
   Briefly explain about the daisy-chaining process of prioritizing interrupts.
   OR
   

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   Explain in detail about interrupt handling.
5. How the pipelining process helps to speed up the processor and discuss the hazards that have to be taken care of in a pipe-lined processor?
   OR
   Why the directory cache coherence protocols are more scalable than snooping cache coherence protocols to achieve the performance?

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