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Download AKTU B-Tech 3rd Sem 2016-2017 NEC 309 Digital Logic Design Question Paper

Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 3rd Semester (Third Semester) 2016-2017 NEC 309 Digital Logic Design Question Paper

This post was last modified on 29 January 2020

AKTU B-Tech Last 10 Years 2010-2020 Previous Question Papers || Dr. A.P.J. Abdul Kalam Technical University


Printed Pages: 7

NEC - 309

(Following Paper ID and Roll No. to be filled in your Answer Books)

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Paper ID: 2289954

Roll No.

B.TECH.

Regular Theory Examination (Odd Sem - III),2016-17

DIGITAL LOGIC DESIGN

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Time: 3 Hours

Max. Marks: 100

Note: Attempt All sections. If require any missing data: then choose suitably.

Section - A

  1. Attempt all questions in brief. (10×2=20)
    1. Perform 2's complement subtraction of 010110-100101.
    2. What is the feature of gray code?
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    4. Write the logic equation and draw the internal logic diagram for a 4 to 1 mux.
    5. What is a priority encoder?
    6. List the major differences between PLA and PAL.
    7. Define a Bus. What are the different types of buses?
    8. Give the comparison between combinational circuits and sequential circuits.
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    10. What are the different types of flip-flop?
    11. Give the comparison between synchronous & asynchronous sequential circuits.
    12. What is Ram? Explain the different types of RAM in detail.
    13. When does race condition occur?
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Section - B

  1. Attempt any three of the following: (3×10=30)
    1. Reduce the Boolean function using k-map technique and implement using gates f (w,x,y,z) = ?m(0,1,4,8,9,10) which has the don't cares condition d(w, x, y, z) = ?m(2,11)
    2. Implement the following multiple output combinational logic circuit using a 3 to 8 decoder.
      1. f1 = ?m(1,2,3,5,7)
      2. f2 = ?m(0,3,6)
      3. f1 = ?m(0,2,4,6)
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      1. Realize a JK flip flop using SR flip flop.
      2. A SR flip flop using NAND gates and explain its operation.

Section - C

  1. Attempt any one part of the following (1×10=10)
    1. Detect and correct error (if any) in the following received even parity Hamming code word 00111101010.
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    3. Minimize the given Boolean function using Quine Mc Clusky method f(A,B,C,D) = ? m(0,1,2,4,5,8,9,11,15) and implement the simplified function using NOR gates only.
  1. Attempt any one part of the following (1×10=10)
      1. Obtain the simplified Boolean expression for the output F and G in terms of the input variables in the circuit of fig. 1
      2. Implement the full adder and full subtractor using decoder.
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      1. Design a combinational circuit that compares the magnitude of two 3 bit numbers and its output indicates whether A>B, A =B, A<B.
      2. Construct a BCD to excess 3 code converter with a 4 bit adder. What must be done to change the circuit to an excess 3 to BCD code converter?
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  1. Attempt any one part of the following (1×10=10)
    1. Design a combinational circuit using a ROM. The circuit accepts a three-bit number and outputs a binary number equal to the square of the input number.
    2. Draw a PLA circuit to implement the functions f1 = A'B + AC' + A'BC', f2 = (AC + AB + BC)', f3 = BC + AC + A'BC'
  1. Attempt any one part of the following (1×10=10)
    1. A sequential circuit has three flip flop A,B and C; one input x in and one output y out. The state diagram is shown in fig2. The circuit is to be designed by treating the unused states as don't-care conditions. Use T flip flop in the design.
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    3. Design a 4 bit binary synchronous counter with D flips flop.
  1. Attempt any one part of the following (1×10=10)
    1. Derive the transition table for the asynchronous sequential circuit shown in fig.3 determine the sequence of internal states Y, Y2 for the following sequence of input XX2: 00,10;,11,01,11,10,00.
    2. An asynchronous sequential circuit is described by the excitation function Y = x^x + (x + x)y and z = y
      1. Draw the logic diagram of the circuit
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      3. Drive the transition table and output map.

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