Download AKTU B-Tech 5th Sem 2015-2016 Integrated Circuits Nec 501 Question Paper

Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 5th Semester (Fifth Semester) 2015-2016 Integrated Circuits Nec 501 Question Paper

Printed Pages : 4 387 NEC-501
(Following Paper ID and Roll No. to be filled in your
Answer Book)
B.Tech
(SEM. V) (ODD SEM)
THEORY EXAMINATION , 2015-16
INTEGRATED CIRCUITS
Time:3 hours] [Maximun?Marks?OO
Section-A
1. Attempt all parts. All parts carry equal marks. Write
answer of each part in short. (2x10=20)
(a) Why don?t we normally realize the beta-
compensated current mirror using MOS?
(b) What are the basic blocks of phase-locked loop?
(c) What do you understand by hysteresis voltage?
((1) What is the role of coupling capacitor (C) in IC
741 internal circuit?
(e) Give the example of a square wave generator which
utilizes positive feedback.
(f) What is capture range in PLL?
(1) NEC-SOl / 11600

(g) What is the chip number for phase locked loop?
(h) De?ne the term Vm and VIL for the CMOS inverter.
(i) The basic step of 9 bit DAC is 10.3mV. if
000000000 represents 0 V, what output is
producedifthe input is 10110111]?
(j) De?ne noise margin for the CMOS inverter.
Section-B
Note: Attempt any ?ve questions from this section.
(10x5=50)
2. What do you understand by the base current compensated
current mirror? How does it provide improvement over
simple current mirror circuit? Expalin with the help of a
neat circuit diagram.
3. De?ne the slew rate. Also derive the relationship between
f?and slew rate for the IC 741.
4. Sketch the properly labeled Master Slave D ?ip-?Op
circuit and explain its operation with the help of proper
waveform of the clock signal.
5. What is a DAC? Describe the weighted resistor DAC.
Give mathematical expressions in support of your
answer.
(2) NEC?SO]
6.
Determine IcL Iczi Ic3 for the circuit shown in ?gure 1.
Assume B = 125 .
1'? 1"? 1'?
I
I
neglected
1.94m
+
Figure 1
Draw the ?mctional block diagram of IC 555 and explain its
working. Design a 555 timer as an Astabel multivibrator with '
an output signal timer frequency of 700 Hz and 60% duty
cycle.
Describe the Antoniou inductance simulation circuit with
properly labelled circuit diagram and give mathematical
expressions in support of your answer.
Describe the sample and hold circuit with the help of an 0p-
amp. What are the applications of sample and hold circuit?
(3) P.T.O.

Section-C
Note: Attempt any two questions from this section.
10.
IL
12.
(15x2=30)
Describe the circuit for the KHN ?lter using three op-amp.
Design a second order butterwonh low-pass ?lter having
upper cut-off frequency lkHz. Determine its frequency
response.
Describe different regions of operation for CMOS inverter '
over its VTC characteristics.
Consider a CMOS inverter {with following parametrs :
VDD = 3.3 V, an = 0.6V, Vmp = 0.7V, Kn = 200/1 A./V2 ,
KP = 80 x1 A/V2
Calculate the noise margin of the CMOS inverter circuit.
Describe the Schmitt trigger with the help of proper circuit
diagram and transfer characteristics. A Schmitt trigger with
the upper threshold level VUT = 0V and hysteresis width is
0.2V converts lkHz sine wave of amplitude 4Vpp into a square
wave. Calculate the time duration of the negative and positive
portion of the output waveform.
?X?
(4) ' NEC?501 / 11600