Download AKTU B-Tech 5th Sem 2015-2016 Integrated Circuits Nec 501 Question Paper

Printed Pages: 4

387

NEC-501

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(Following Paper ID and Roll No. to be filled in your Answer Book)

Paper ID :131501

Roll No.

B.Tech

(SEM. V) (ODD SEM)

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THEORY EXAMINATION, 2015-16

INTEGRATED CIRCUITS

Time:3 hours] [Maximum Marks:100

Section-A

1. Attempt all parts. All parts carry equal marks. Write answer of each part in short. (2x10=20)

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1. Why don't we normally realize the beta-compensated current mirror using MOS?
2. What are the basic blocks of phase-locked loop?
3. What do you understand by hysteresis voltage?
4. What is the role of coupling capacitor (C) in IC 741 internal circuit?
5. Give the example of a square wave generator which utilizes positive feedback.

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6. What is capture range in PLL?
7. What is the chip number for phase locked loop?
8. Define the term VIH and VIL for the CMOS inverter.
9. The basic step of 9 bit DAC is 10.3mV. if 000000000 represents 0 V, what output is produced if the input is 101101111?
10. Define noise margin for the CMOS inverter.

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Section-B

Note: Attempt any five questions from this section. (10x5=50)

2. What do you understand by the base current compensated current mirror? How does it provide improvement over simple current mirror circuit? Explain with the help of a neat circuit diagram.
3. Define the slew rate. Also derive the relationship between f and slew rate for the IC 741.
4. Sketch the properly labeled Master Slave D flip-flop circuit and explain its operation with the help of proper waveform of the clock signal.

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5. What is a DAC? Describe the weighted resistor DAC. Give mathematical expressions in support of your answer.
6. Determine Ic1 Ic2 Ic3 for the circuit shown in figure 1. Assume ß = 125.
7. Draw the functional block diagram of IC 555 and explain its working. Design a 555 timer as an Astable multivibrator with an output signal timer frequency of 700 Hz and 60% duty cycle.
8. Describe the Antoniou inductance simulation circuit with properly labelled circuit diagram and give mathematical expressions in support of your answer.
9. Describe the sample and hold circuit with the help of an op-amp. What are the applications of sample and hold circuit?

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Section-C

Note: Attempt any two questions from this section. (15x2=30)

10. Describe the circuit for the KHN filter using three op-amps. Design a second order Butterworth low-pass filter having upper cut-off frequency 1kHz. Determine its frequency response.
11. Describe different regions of operation for CMOS inverter over its VTC characteristics. Consider a CMOS inverter with following parameters : VDD = 3.3 V, VTO.n = 0.6V, VTO.p = -0.7V, K1 = 200 µ ?/V2, ?1 = 80 µ ?/V2 Calculate the noise margin of the CMOS inverter circuit.
12. Describe the Schmitt trigger with the help of proper circuit diagram and transfer characteristics. A Schmitt trigger with the upper threshold level VUT = 0V and hysteresis width is 0.2V converts 1kHz sine wave of amplitude 4V into a square wave. Calculate the time duration of the negative and positive portion of the output waveform.

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