Download AKTU B-Tech 7th Sem 2018-2019 NEC 703 Vlsi Design Question Paper

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Paper Id: 130718

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B. TECH

Roll No.

Sub Code:NEC703

(SEM-VII) THEORY EXAMINATION 2018-19

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VLSI DESIGN

Time: 3 Hours

Total Marks: 100

Note: 1. Attempt all Sections. If require any missing data; then choose suitably.

SECTION A

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1. Attempt all questions in brief. 2 x 10 = 20

1. Why we need a low power VLSI circuits in today's scenario?
2. Explain the terms packaging and testing.
3. Define logical effort with example.
4. Define the terms- Defects, Errors and Faults.

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5. Distinguish between SRAM and DRAM.
6. Bring out the drawbacks of dynamic logic.
7. Explain the term controllability and observability.
8. Why we prefer CMOS transmission gates over other gates?
9. Define the term Interconnect.

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10. What is meant by Stuck-at-1(s-a-1) faults.

SECTION B

2. Attempt any three of the following: 10 x 3 = 30

1. Illuminate the n-well CMOS fabrication process with neat diagrams.
2. Write short note on:
   1. Logical Effort

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   2. Parasitic Delay
3. Explain the Elmore Delay Model with suitable diagram.
4. Enlist the advantages of dynamic logic circuit over static logic circuit.
5. Explain the NORA CMOS logic circuit with suitable example. Describe leakage power dissipation and dynamic power dissipation.

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SECTION C

Attempt any one part of the following: 10 x 1 = 10

4.

1. 1. Write short note on VLSI testing.
   2. Draw and explain the VLSI design Flow(Y-chart).

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2. Draw and explain the working of CMOS inverter with its transfer characteristics.

Attempt any one part of the following: 10 x 1 = 10

5.

1. Analyze the Linear delay model with its different limitations.

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2. Explain the following circuits:
   1. Variable threshold CMOS circuits
   2. Multiple threshold CMOS circuits

Attempt any one part of the following: 10 x 1 = 10

6.

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1. Draw and explain the working of Lumped RC-model for interconnects.
2. Explain the Delay Estimation with different optimization techniques.

7. Attempt any one part of the following: 10 x 1 = 10

1. Explain read/write operation of SRAM memory cell. How 1-bit cell is used in bigger memory systems.
2. 1. Implement the Boolean function Y = AB + (C+D)(F+E)+GH using DOMINO CMOS logic.

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   2. Explain the term Voltage Boot Strapping in CMOS logic with suitable examples.

8. Attempt any one part of the following: 10 x 1 = 10

1. Explain the issues involved in Built-in Self Test (BIST) techniques in detail.
2. 1. Write a short note on Adiabatic Logic Circuit.

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   2. Explain the Scan Based Techniques.

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