Download AKTU B-Tech 7th Sem 2018-2019 NEC 703 Vlsi Design Question Paper

Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 7th Semester (Seventh Semester) 2018-2019 NEC 703 Vlsi Design Question Paper

Printed Pa_es: 02 Sub CodezNEC703
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B. TECH
(SEM-VII) THEORY EXAMINATION 2018-19
VLSI DESIGN
T ime: 3 Hours - T otal Marks: 100
Note: 1. Attempt all Sections. If require any missing data; then choose suitably.
SECTION A
1. Attempt all questions in brief. 2 x 10 = 20
Why we need a low power VLSI circuits in today?s scenario?
Explain the terms packaging and testing.
De?ne logical effort with example.
Define the terms- Defects, Errors and Faults.
Distinguish between SRAM and DRAM. ?
Bring out the drawbacks of dynamic logic.
Explain the term controllability and observability
Why we prefer CMOS transmission gates over other gates?
De?ne the term Interconnect. a:
What 15 meant by Stuck-at-l(s?a-1) fanmand Stuck?at-O(s- -a- 0) faults.
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a. Illuminate the n-well CMOSkbricatlon process with neat diagram5,; 5 ?
b. Explain the Elmore Delay M6del with suitable diagram "* ?:4 i
0. Write short note on:
(i) Logical Effort
(ii) Paramii} Delay
d. Enlist the acgyhhtages of dynamic logic circuit over 5tatie l6gic circuit. Explain
NORA CMOS logic circuit with suitable example
2. Attempt any three of the following:
e. Describe leakage power dissipation and dynamic power dissipation.
SECTION C 5 5 5 ?
3. Attempt any one part of the following: 10 x 1 = 10
(a) (i)Write short note on VLSI testing: '; i 3
(ii) Draw and explain the VLSI dgsgig?: Flow(Y- chart).
(b) Draw and explain the working of CMOS inverter with its transfer
characteristics. ? s
4. Attempt any one part of the fo?oyhig 10 x 1 = 10
(a) Analyze the Linear defay ni6del with its different limitations
(b) Explain the following circuits:
(i) Variable?threshold CMOS circuits
(ii) Multiple threshold CMOS circuits
5. Attempt any one part of the following: 10 x 1 = 10
(a) Draw and explain the working of Lumped RC-model for interconnects.
(b) Explain the Delay Estimation with different optimization techniques.
MAMSH KUMAR JHA I 11-Dec-2018 13:31:13 I 117.55.242.131

6. Attempt any one part of the following: 10 x 1 = 10
(a) Explain read/W?rite operation of SRAM memory cell. How 1?bit cell is used in
bigger memory systems.
(b) (i) Implement the Boolean function Y = AB + (C+D)(F+E)+GH using
DOMINO CMOS logic.
(ii) Explain the term Voltage Boot Strapping in CMOS logic with suitable
examples.
7. Attempt any one part of the following: 10 x 1 = 10
(a) Explain the issues involved in Built-in Self Test (BIST) techniques in detail.
(b) (i) Write a short note on Adiabatic Logic Circuit.
(ii) Explain the Scan Based Techniques.
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MANISH KUMAR JHA | 17-Dec-2018 13:31 :13 I 1115524113?!