Download AKTU B-Tech 8th Sem 2016-17 Digital System Design Using Vhdl Question Paper

Download AKTU (Dr. A.P.J. Abdul Kalam Technical University (AKTU), formerly Uttar Pradesh Technical University (UPTU) B-Tech 8th Semester (Eight Semester) 2016-17 Digital System Design Using Vhdl Question Paper

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B. TECH.
THEORY EXAMINATION (SEM?VIII) 2016-17
DIGITAL SYSTEM DESIGN USING VHDL
T ime : 3 Hours Max. Marks : 100
Note .' Be precise in your answer. In case ofnumericalproblem assume data wherever not provided.
SECTION-A
Explain the following: (10X2=20)
Generics.
Concurrent statements and Sequential statements.
Array and Records types.
Function and Procedure.
Packages and Library.
Process and Wait statement.
Conditional and Case statement.
Structural Modelling.
Transport and Delta Delay.
HDL design ?ow for synthesis.
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SECTION-B
Attempt any ?ve of the following: (10X5=50)
a. Draw block diagram for UART and SM chart for UART transmitter and discuss the VHDL
code for UART transmitter.
b. What is the various ?oating operation? Draw and explain the ?ow chart for ?oating point
multiplication.
Write a high level VHDL description of the divider.
Write a short note on synthesis of VHDL codes.
Draw a state graph for 4X4 binary multiplier control and discuss the behavioral VHDL model.
Using block diagram explain compilation elaboration and simulation of VHDL code. Write a
VHDL description of an SR latch use two logic gates.
g. Write a VHDL code for a full subtractor using logic equation.
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SECTION-C
Attempt any two of the following: (15X2=30)
3. Write down the truth table, working of a 16 X 1 multiplexer along with its diagram. Implement
16 x 1 multiplexer in VHDL using case statement with suitable diagram.
4. Write down the VHDL code for ALU and describe it?s working. Brie?y explain the function of
control unit with suitable diagram.
Write short note on the followings with suitable diagram:
FPGA.
CPLD
PLA and PAL
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