Download AKTU B-Tech 8th Sem 2016-17 Digital System Design Using Vhdl Question Paper

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Time: 3 Hours

B. TECH.

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THEORY EXAMINATION (SEM–VIII) 2016-17

DIGITAL SYSTEM DESIGN USING VHDL

Max. Marks : 100

Note : Be precise in your answer. In case of numerical problem assume data wherever not provided.

SECTION-A

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1. Explain the following: (10×2=20)

1. a. Generics.
2. b. Concurrent statements and Sequential statements.
3. c. Array and Records types.
4. d. Function and Procedure.

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5. e. Packages and Library.
6. f. Process and Wait statement.
7. g. Conditional and Case statement.
8. h. Structural Modelling.
9. i. Transport and Delta Delay.

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10. j. HDL design flow for synthesis.

SECTION-B

2. Attempt any five of the following: (10×5=50)

1. a. Draw block diagram for UART and SM chart for UART transmitter and discuss the VHDL code for UART transmitter.
2. b. What is the various floating operation? Draw and explain the flow chart for floating point multiplication.

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3. c. Write a high level VHDL description of the divider.
4. d. Write a short note on synthesis of VHDL codes.
5. e. Draw a state graph for 4x4 binary multiplier control and discuss the behavioral VHDL model.
6. f. Using block diagram explain compilation elaboration and simulation of VHDL code. Write a VHDL description of an SR latch using two logic gates.
7. g. Write a VHDL code for a full subtractor using logic equation.

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SECTION-C

Attempt any two of the following: (15×2=30)

1. 3. Write down the truth table, working of a 16 x 1 multiplexer along with its diagram. Implement 16 x 1 multiplexer in VHDL using case statement with suitable diagram.
2. 4. Write down the VHDL code for ALU and describe its working. Briefly explain the function of control unit with suitable diagram.
3. 5. Write short note on the followings with suitable diagram:
   1. a. FPGA.

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   2. b. CPLD
   3. c. PLA and PAL

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