Download JNTUA M.Tech 1st Sem 2017 Feb 9D06106b DSP Processors And Architectures Question Paper

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Code: 9D06106b

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M.Tech I Semester Regular & Supplementary Examinations January/February 2017

DSP PROCESSORS & ARCHITECTURES

(Common to DSCE, DECS & ECE)

Time: 3 hours

Max. Marks: 60

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Answer any FIVE questions

All questions carry equal marks

1. For the FIR filter Y[n] = [x(n) + x(n-1) + x(n-2)]/3. Determine:

   1. System response function.
   2. Phase response function.

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   3. Magnitude response function.
2. 1. Write notes on A/D conversion errors.
   2. Find the decimal equivalent of the floating point number 1011000011100. Assume a format similar to IEEE-754 in which the MSB in the sign bit followed by 4 exponent bits followed by 8 bits for the fractional part.

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3. 1. Design a 4X4 barrel shifter with neat diagrams.
   2. Explain in detail about on chip memory.
4. 1. Explain the concept of pipelining with various stages with an example.
   2. Explain about interlocking.

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5. 1. Explain the interrupts of TMS 320C54XX processors.
   2. Explain in detail about on chip periphera
6. 1. Write notes on adaptive filters.

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   2. Represent each of the following as 16 bit numbers in the desired Q-notation.

   Determine the following:

   1. 0.3125 as Q15 number.
   2. -0.3125 as a Q15 number.

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7. 1. Number of stages for a 128 point FFT computation:
   2. Number of butterflies needed for the entire computation.
   3. Number of butterflies that require real twiddle factors.
8. How does DMA helps in increasing the processing speed of a DSP processor?

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