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Download JNTUA M.Tech 1st Sem 2018 Regular Feb 9D06101 Digital System Design Question Paper

Download JNTUA (JNTU Anantapur) M.Tech ( Master of Technology) 1st Semester 2018 Regular Feb 9D06101 Digital System Design Previous Question Paper

This post was last modified on 30 July 2020

This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)


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Code: 9D06101

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M.Tech I Semester Supplementary Examinations February/March 2018

(Common to DSCE, DECS, ECE, VLSIES, ESVLSI, VLSIESD & MNE)

(For students admitted in 2012, 2013, 2014, 2015 & 2016 only)

Time: 3 hours

DIGITAL SYSTEM DESIGN

Max. Marks: 60

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Answer any FIVE questions

All questions carry equal marks


  1. Draw an ASM chart to design a control logic of a binary multiplier. Realize the same using MUX, decoder and D-type flip flops.
  2. Design a sequential circuit to convert excess 3 to BCD code using PLA and D flip-flops.
  3. (a) Explain in detail the path-sensitization technique with an example.

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    (b) Define Kohavi algorithm. Explain this algorithm with an example.
  4. (a) Describe the algorithmic steps involved in PODEM with an example.
    (b) Write a brief note on random testing.
  5. Explain in detail about state identification and fault diagnosis in a sequential circuit.
  6. (a) Realize the following expression using PLA. f = x'y'z + x'yz + xyz + xy'z' and explain PLA minimization.

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    (b) What is the need for PLA folding and describe in detail PLA folding with examples?
  7. Explain different types of fault models and fault types in a PLA.
  8. Write a short note on:
    (a) Minimal closed covers.
    (b) Cycles and races.
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This download link is referred from the post: JNTUA M.Tech 1st Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)

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