Download JNTUA M.Tech 2nd Sem 2017 Feb 9D06203 Design of Fault Tolerant Systems Question Paper

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Code: 9D06203

Max. Marks: 60

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Time: 3 hours

M.Tech II Semester Supplementary Examinations January/February 2017

DESIGN OF FAULT TOLERANT SYSTEMS

(Digital Systems and Computer Electronics)

Answer any FIVE questions

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All questions carry equal marks

1. 1. Derive the relationship between reliability and mean time between failures (MTBF).
   2. Derive the expression for reliability of a parallel combinational circuit.
2. 1. With a neat diagram, discuss about Sift-out redundancy technique.

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   2. Discuss about static and dynamic redundant systems with necessary diagrams.
3. Design a self checking checker using Berger code with an example.
4. Design a sequential circuit for fail-safe design using partition theory.
5. Discuss about an LFSR based signature analyzer with a neat diagram.

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6. Discuss the design of a combinational circuit for testability using control and syndrome testable design.
7. Explain how controllability and observability are obtained by means of scan register with an example.
8. Discuss about test pattern generation for BIST exhaustive testing with an example.

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