Download JNTUA M.Tech 2nd Sem 2017 Feb 9D06206b Algorithms for VLSI Design Automation Question Paper

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Code: 9D06206b

Max. Marks: 60

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Time: 3 hours

M.Tech II Semester Supplementary Examinations January/February 2017

ALGORITHMS FOR VLSI DESIGN AUTOMATION

(Digital Systems & Computer Electronics)

Answer any FIVE questions

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All questions carry equal marks

1. 1. List and explain any two design automation tools.
   2. How graph theory is useful for VLSI design automation.
2. 1. Why combinational optimization is required? Explain the principle of backtracking.

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   2. How combinatorial optimization is achieved using local & Tabu search.
3. 1. Explain the concept of layout compaction bringing out clearly, how compaction is useful for VLSI design.
   2. Explain the routing problems in floor planning methods of VLSI design.

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4. 1. Explain how gate level modeling is inferior/superior to switch level modeling.
   2. Write about the compiler-driven simulation.
5. 1. Explain the basic issues and terminology involved in logic synthesis and verification.
   2. Explain two-level logic synthesis with suitable examples.

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6. 1. How allocation, assignment and scheduling are done in high level synthesis?
   2. Explain high level transformations related to high level synthesis.
7. 1. Explain the physical design cycle of FPGA.

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   2. Explain about partitioning for segmented models.
8. Explain briefly:
   1. MCM physical design cycle.
   2. Maze routing.
   3. Programmable MCM.

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