Subject Code: 2161101
GUJARAT TECHNOLOGICAL UNIVERSITY
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BE - SEMESTER- VI EXAMINATION — SUMMER 2020Subject Name: VLSI Technology & Design
Time: 10:30 AM TO 01:00 PM
Instructions:
- Attempt all questions.
- Make suitable assumptions wherever necessary.
- Figures to the right indicate full marks.
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Q1 (a) Compare: Semi-custom and Full custom VLSI design style. 03
(b) Write a short note on CMOS ring oscillator circuit. 04
(c) List out the fabrication steps of nMOS transistor with necessary figures. 07
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Q2 (a) Define the following terms with example: (1) Controllability (2) Observability. 03
(b) What is substrate bias effect? Derive the expression for the threshold voltage. 04
(c) Draw and discuss: The circuit diagram of domino CMOS logic gate. 07
OR
(c) Draw and explain: CMOS implementation of D latch with two inverter and two CMOS TG gates. 07
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Q3 (a) Explain latch-up problem observed in CMOS circuits. How it can be avoided? 03
(b) Explain the energy band diagram of MOS structure at surface inversion and derive the expression for the maximum possible depth of the depletion region. 04
(c) Measured voltage and current data for a MOSFET are given below. Determine the type of the device, and calculate the parameters kn, VT0, and ?. Assume FF =-0.3 V. 07
| VGS(V) | VDS(V) | VSB(V) | ID(µA) |
|---|---|---|---|
| 3 | 3 | 0 | 97 |
| 3 | 3 | 1 | 59 |
| 3 | 5 | 0 | 97 |
| 3 | 5 | 1 | 59 |
| 4 | 3 | 0 | 235 |
| 4 | 3 | 1 | 173 |
| 4 | 5 | 0 | 235 |
| 4 | 5 | 1 | 173 |
| 5 | 3 | 0 | 433 |
| 5 | 3 | 1 | 347 |
| 5 | 5 | 0 | 433 |
| 5 | 5 | 1 | 347 |
OR
(a) Draw the inverter circuit with Resistive Load. Derive critical voltage points VOH and VOL for Resistive Load inverter circuit. 03
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(b) Explain the basic principles of pass transistor circuits. Also explain logic “0” and logic “1” transfer. 04(c) Calculate the average junction capacitance for a simple abrupt pn-junction, which is reverse biased with a voltage Vbias. The doping density of the n-type region is ND = 1016 cm-3, and the doping density of the p-type region is NA = 1018 cm-3. The junction area is A=20µm x 20µm. Assume that the reverse bias voltage changes from 0 to -5V. 07
Date:02/11/2020
Total Marks: 70
Q.4 (a) Briefly explain working of FPGA with suitable diagram. 03
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(b) Explain voltage bootstrapping in brief. 04(c) Consider a resistive-load inverter circuit with VDD=5V, kn=20 µA/V2, VT0=0.8V, RL=200kO, and W/L=2. Calculate the critical voltages VOL, VOH, VIL & VIH on the VTC and find the noise margins of the circuit. 07
OR
(a) Explain Built-in Self Test (BIST) techniques in brief. 03
(b) Write a short note on switching power dissipation of CMOS inverters. 04
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(c) Consider a depletion-load inverter circuit with VDD=5V, VT0,driver = 1V, VT0,load = -3V, (W/L)driver = 2, (W/L)load = 1/3, kn,driver = kn,load = 25 uA/V2, ? = 0.4 V1/2 and F = -0.3 V. Calculate the critical voltages VOL, VOH, VIL & VIH on the VTC and find the noise margins of the circuit. 07Q.5 (a) Write a short note on behavior of bistable elements. 03
(b) Realize the following Boolean function: 04
(1) F=AB + A’C’ + AB’C using CMOS Transmission Gates.
(2) F=[(C+D+E)·(B+A)]’ using CMOS.
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(c) In CMOS inverter circuit, define propagation delay tPLH and obtain its expression. 07OR
(a) Explain CMOS Transmission gate in brief. 03
(b) Draw voltage transfer characteristics of CMOS inverter and define VIL, VIH, VOL, VOH, NML and NMH. 04
(c) Draw Y- Chart for VLSI design. Also list out possible physical faults, electrical faults and logical faults in the circuit. 07
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