Download GTU (Gujarat Technological University Ahmedabad) B.Tech/BE (Bachelor of Technology/ Bachelor of Engineering) 2020 Summer 6th Sem 2161101 Vlsi Technology And Design Previous Question Paper

Enrolment No.___________

**GUJARAT TECHNOLOGICAL UNIVERSITY**

**BE - SEMESTER? VI EXAMINATION ? SUMMER 2020**

**Subject Code: 2161101**

**Date:02/11/2020**

**Subject Name: VLSI Technology & Design**

**Time: 10:30 AM TO 01:00 PM**

**Total Marks: 70**

**Instructions:**

**1. Attempt all questions.**

**2. Make suitable assumptions wherever necessary.**

**3. Figures to the right indicate full marks.**

**MARKS**

**Q.1**

**(a)**Compare: Semi-custom and Full custom VLSI design style.

**03**

**(b)**Write a short note on CMOS ring oscillator circuit.

**04**

**(c)**List out the fabrication steps of nMOS transistor with necessary

**07**

figures.

**Q.2**

**(a)**Define the following terms with example: (1) Controllability (2)

**03**

Observability.

**(b)**What is substrate bias effect? Derive the expression for the threshold

**04**

voltage.

**(c)**Draw and discuss: The circuit diagram of domino CMOS logic gate.

**07**

**OR**

**(c)**Draw and explain: CMOS implementation of D latch with two

**07**

inverter and two CMOS TG gates.

**Q.3**

**(a)**Explain latch-up problem observed in CMOS circuits. How it can be

**03**

avoided?

**(b)**Explain the energy band diagram of MOS structure at surface

**04**

inversion and derive the expression for the maximum possible depth

of the depletion region.

**(c)**Measured voltage and current data for a MOSFET are given below.

**07**

Determine the type of the device, and calculate the parameters kn,

VT0, and . Assume ?F = -0.3 V.

VGS(V) VDS(V) VSB(V) ID(?A)

3

3

0

97

4

4

0

235

5

5

0

433

3

3

3

59

4

4

3

173

5

5

3

347

**OR**

**Q.3**

**(a)**Draw the inverter circuit with Resistive Load. Derive critical voltage

**03**

points VOH and VOL for Resistive Load inverter circuit.

**(b)**Explain the basic principles of pass transistor circuits. Also explain

**04**

logic "0" and logic "1" transfer.

**(c)**Calculate the average junction capacitance for a simple abrupt pn-

**07**

junction, which is reverse biased with a voltage Vbias. The doping

density of the n-type region is ND = 1019 cm-3, and the doping density

of the p-type region is NA = 1016 cm-3. The junction area is

A=20?m?20?m. Assume that the reverse bias voltage changes from

0 to -5V.

1

**Q.4**

**(a)**Briefly explain working of FPGA with suitable diagram.

**03**

**(b)**Explain voltage bootstrapping in brief.

**04**

**(c)**Consider a resistive-load inverter circuit with V

'

DD=5V, kn =20 ?A/V2,

**07**

VT0

**=**0.8V, RL=200k, and W/L=2. Calculate the critical voltages

VOL, VOH, VIL & VIH on the VTC and find the noise margins of the

circuit.

**OR**

**Q.4**

**(a)**Explain Built-in Self Test (BIST) techniques in brief.

**03**

**(b)**Write a short note on switching power dissipation of CMOS

**04**

inverters.

**(c)**Consider a depletion-load inverter circuit with VDD=5V, VT0,driver

**07**

=1V, VT0,load = -3V, (W/L)driver = 2, (W/L)load = 1/3, kn,driver' = kn,load' =

25 ?A/V2, = 0.4 V1/2 and ?F = -0.3 V. Calculate the critical voltages

VOL, VOH, VIL & VIH on the VTC and find the noise margins of the

circuit.

**Q.5**

**(a)**Write a short note on behavior of bistable elements.

**03**

**(b)**Realize the following Boolean function:

**04**

(1) F = AB + A'C' + AB'C using CMOS Transmission Gates.

(2) F = [(C+D+E)?(B+A)]' using CMOS.

**(c)**In CMOS inverter circuit, define propagation delay PLH and obtain

**07**

its expression.

**OR**

**Q.5**

**(a)**Explain CMOS Transmission gate in brief.

**03**

**(b)**Draw voltage transfer characteristics of CMOS inverter and define

**04**

VIL, VIH, VOL, VOH, NML and NMH.

**(c)**Draw Y- Chart for VLSI design. Also list out possible physical faults,

**07**

electrical faults and logical faults in the circuit.

*****************

2

This post was last modified on 04 March 2021