Download Anna University B.Tech (Bachelor of Technology) CSE (Computer Science And Engineering) 3rd Sem CS8382 Digital Systems DS Lab Manual Question Paper.

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

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1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

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1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections were given as per circuit diagram.

2. Logical inputs were given as per truth table

3. Observe the logical output and verify with the truth tables.

Result:

Thus the code converters were designed and verified using the corresponding truth table.

Outcome:

At the completion of an experiment student will able to design the binary to gray converter.

1. What is binary code?

2. What is gray code?

3. What are the advantages of gray code?

4. What is unit distance code?

5. What is sequential code?

6. How to convert binary to gray code?

7. How to convert gray to binary code?

8. What is reflective code?

9. What are the advantages of EX ? 3 code?

10. Which code is used to arithmetic operation in digital circuits?

11. Explain the operation of EX ? OR.

12. What is K ? Map?

13. Draw the truth table of EX- OR gate.

14. What is SOP?

15. What is POS?

16. What is minterm?

Viva ? Voce

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections were given as per circuit diagram.

2. Logical inputs were given as per truth table

3. Observe the logical output and verify with the truth tables.

Result:

Thus the code converters were designed and verified using the corresponding truth table.

Outcome:

At the completion of an experiment student will able to design the binary to gray converter.

1. What is binary code?

2. What is gray code?

3. What are the advantages of gray code?

4. What is unit distance code?

5. What is sequential code?

6. How to convert binary to gray code?

7. How to convert gray to binary code?

8. What is reflective code?

9. What are the advantages of EX ? 3 code?

10. Which code is used to arithmetic operation in digital circuits?

11. Explain the operation of EX ? OR.

12. What is K ? Map?

13. Draw the truth table of EX- OR gate.

14. What is SOP?

15. What is POS?

16. What is minterm?

Viva ? Voce

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections were given as per circuit diagram.

2. Logical inputs were given as per truth table

3. Observe the logical output and verify with the truth tables.

Result:

Thus the code converters were designed and verified using the corresponding truth table.

Outcome:

At the completion of an experiment student will able to design the binary to gray converter.

1. What is binary code?

2. What is gray code?

3. What are the advantages of gray code?

4. What is unit distance code?

5. What is sequential code?

6. How to convert binary to gray code?

7. How to convert gray to binary code?

8. What is reflective code?

9. What are the advantages of EX ? 3 code?

10. Which code is used to arithmetic operation in digital circuits?

11. Explain the operation of EX ? OR.

12. What is K ? Map?

13. Draw the truth table of EX- OR gate.

14. What is SOP?

15. What is POS?

16. What is minterm?

Viva ? Voce

41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.8: PARITY GENERATORS AND CHECKERS

Aim:

To implement the odd and even parity checkers using the logic gates and also to generate the odd parity

and even parity numbers using the generators

Apparatus required:

Sl. No Component Type Quantity

1 Trainer Kit - 1

2 EX-OR IC7486 1

3 NOT gate IC 7404 1

4 Connecting wires - Required

Theory:

Parity checking is used for error detection in data transmission.

Odd parity checkers:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

odd.

Even parity checker:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

even.

Odd parity generators:

It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also

the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits

which is an odd parity number.

Even parity generator:

It generates an even parity number. The even parity checker circuit is used with the inverted output and

also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5

bits which is an even parity number.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A 12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections were given as per circuit diagram.

2. Logical inputs were given as per truth table

3. Observe the logical output and verify with the truth tables.

Result:

Thus the code converters were designed and verified using the corresponding truth table.

Outcome:

At the completion of an experiment student will able to design the binary to gray converter.

1. What is binary code?

2. What is gray code?

3. What are the advantages of gray code?

4. What is unit distance code?

5. What is sequential code?

6. How to convert binary to gray code?

7. How to convert gray to binary code?

8. What is reflective code?

9. What are the advantages of EX ? 3 code?

10. Which code is used to arithmetic operation in digital circuits?

11. Explain the operation of EX ? OR.

12. What is K ? Map?

13. Draw the truth table of EX- OR gate.

14. What is SOP?

15. What is POS?

16. What is minterm?

Viva ? Voce

41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.8: PARITY GENERATORS AND CHECKERS

Aim:

To implement the odd and even parity checkers using the logic gates and also to generate the odd parity

and even parity numbers using the generators

Apparatus required:

Sl. No Component Type Quantity

1 Trainer Kit - 1

2 EX-OR IC7486 1

3 NOT gate IC 7404 1

4 Connecting wires - Required

Theory:

Parity checking is used for error detection in data transmission.

Odd parity checkers:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

odd.

Even parity checker:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

even.

Odd parity generators:

It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also

the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits

which is an odd parity number.

Even parity generator:

It generates an even parity number. The even parity checker circuit is used with the inverted output and

also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5

bits which is an even parity number.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C? + ABC = A B C

Carry:

CARRY = AB + AC + BC

Logic Diagram:

18 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagrams.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Result:

The design of the half adder and full adder circuits was done and their truth tables were verified.

Outcome:

At the completion of an experiment student will able to design the half adder circuit and the

full adder circuit.

19 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.4: HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and verify the truth table of the half subtractor & full subtractor circuits

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The subtraction of two binary digits has four possible operations. In all operations, each subtrahend bit

is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

Half subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

Full subtractor:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.

From the truth table the expression for difference and borrow bits of the output can be obtained

as,

Difference, DIFF= A?B?C + A?BC? + AB?C? + ABC

Borrow, BORR = A?BC + AB?C + ABC? +ABC

20 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half subtractor

Truth table:

Sl.No. Input Output

A B Difference Borrow

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A?. B

Logic diagram:

2. Full subtractor

Truth table:

Sl.No.

Input Output

A B C Difference Borrow

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

21 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Difference

Difference = A?B?C + A?BC? + AB?C? + ABC

Borrow

Borrow = A?B + A?C + BC

Circuit diagram:

22 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.5: 4-BIT ADDER AND SUBTRACTOR

Aim:

To design and implement 4-bit adder and subtractor using IC 7483

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. IC IC 7483 1

3. NOT gate IC 7404 1

4. EX-OR gate IC 7486 1

5. Connecting wires As required

Theory:

4 BIT Binary adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be

constructed with full adders connected in cascade, with the output carry from each full adder connected to

the input carry of next full adder in chain. The augends bits of ?A? and the addend bits of ?B? are

designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The

carries are connected in chain through full adder. The input carry to the adder is C

0

and it ripples through

the full adder to the output carry C

4

.

4 BIT Binary subtractor:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input

?B? and the corresponding input of full adder. The input carry C

0

must be equal to 1 when performing

subtraction.

4 BIT Binary adder / subtractor:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it

becomes subtractor.

23 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PIN Diagram for IC 7483:

Logic Diagram: 4-Bit Binary Diagram:

Logic diagram: 4-Bit Binary Subtractor:

4-Bit Binary Adder /Subtractor:

24 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Procedure:

1. Connections are given as per the circuit diagrams.

2. Logical inputs were given as per circuit diagram.

3. Apply the inputs and verify the truth table for the 4-bit adder and subtractor.

.

Result:

The design of the 4-bit Binary adder and l subtractor circuit was done and its truth table was

verified.

Outcome:

At the completion of an experiment student will able to design 4-bit binary adder and subtractor

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

25 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is expression for difference and borrow?

2. Write the truth table for half adder.

3. Write the truth table for full adder.

4. Write the truth table for half subtrator.

5. Write the truth table for full subtrator.

6. Draw the logic diagram of full subtrator.

7. What is adder?

8. List out the application of adders.

9. Draw the full adder using two half adder circuits.

10. What is combinational circuit?

11. What is different between combinational and sequential circuit?

12. What are the gates involved for binary adder?

13. List the properties of Ex-Nor gate?

14. What is expression for sum and carry?

Viva ? Voce

26 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.6: MAGNITUDE COMPARATOR

Aim:

To design, construct and study the performance of 2 bit magnitude comparator

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The comparison of two numbers is an operator that determines one number is greater than, less

than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by

three binary variables that indicate whether A>B, A=B (or) A

Truth table:

27 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K-map

28 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

Pin Diagram for IC 7485:

Logic Diagram:

29 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

8 Bit Magnitude Comparator:

Truth table:

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Result:

Thus the 2-bit and 8-bit magnitude comparator was designed and verified using the logic gates.

Outcome:

At the completion of an experiment student will able to design the 2-bit and 8-bit magnitude

comparator using logic gates.

A B A>B A=B A

**0 0 0 0**

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0

0 0 0 1

0 0 0 1

0 0 0 0

0 0 0 0

1 0 0

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1

Viva ? Voce

30 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

1. What is magnitude comparator?

2. What is most significant bit?

3. Explain operation of AND gate.

4. Explain truth table of a comparator.

5. Explain magnitude comparator7485 IC.

6. What is 8-bit input Magnitude Comparator?

7. What is IC?

8. Explain the k-map simplification of A>B.

9. Explain the k-map simplification of A=B.

10. Explain the k-map simplification of A

**11. Draw the logic diagram of 1-bit magnitude comparator.**

12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections were given as per circuit diagram.

2. Logical inputs were given as per truth table

3. Observe the logical output and verify with the truth tables.

Result:

Thus the code converters were designed and verified using the corresponding truth table.

Outcome:

At the completion of an experiment student will able to design the binary to gray converter.

1. What is binary code?

2. What is gray code?

3. What are the advantages of gray code?

4. What is unit distance code?

5. What is sequential code?

6. How to convert binary to gray code?

7. How to convert gray to binary code?

8. What is reflective code?

9. What are the advantages of EX ? 3 code?

10. Which code is used to arithmetic operation in digital circuits?

11. Explain the operation of EX ? OR.

12. What is K ? Map?

13. Draw the truth table of EX- OR gate.

14. What is SOP?

15. What is POS?

16. What is minterm?

Viva ? Voce

41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.8: PARITY GENERATORS AND CHECKERS

Aim:

To implement the odd and even parity checkers using the logic gates and also to generate the odd parity

and even parity numbers using the generators

Apparatus required:

Sl. No Component Type Quantity

1 Trainer Kit - 1

2 EX-OR IC7486 1

3 NOT gate IC 7404 1

4 Connecting wires - Required

Theory:

Parity checking is used for error detection in data transmission.

Odd parity checkers:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

odd.

Even parity checker:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

even.

Odd parity generators:

It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also

the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits

which is an odd parity number.

Even parity generator:

It generates an even parity number. The even parity checker circuit is used with the inverted output and

also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5

bits which is an even parity number.

42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Input Checker output Generator output

A B C D D odd even odd even

0 0 0 1 1 0 00010 00011

0 0 1 0 1 0 00100 00101

0 0 1 1 0 1 00111 00110

0 1 0 0 1 0 01000 01001

0 1 0 1 0 1 01011 01010

0 1 1 0 0 1 01101 01100

0 1 1 1 1 0 01110 01111

1 0 0 0 1 0 10000 10001

1 0 0 1 0 1 10011 10010

1 0 1 0 0 1 10101 10100

1 0 1 1 1 0 10110 10111

1 1 0 0 0 1 11001 11000

1 1 0 1 1 0 11010 11011

1 1 1 0 1 0 11100 11101

1 1 1 1 0 1 11111 11110

Procedure:

1. The circuit is implemented using logic gates.

2. The inputs are given as per the truth table.

3. The corresponding outputs are noted.

4. The theoretical and practical values were verified.

Result:

The odd and even parity checkers are implemented using the logic gates and the odd parity and

even parity numbers are generated using the corresponding generators.

Outcome:

At the completion of an experiment student will able to verify the odd and even parity checker

using logic gates.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

2 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

3 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

4 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

5 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

6 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

7 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

8 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

9 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

10 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

NAND Gate symbol: PIN Diagram:

NOR Gate:

11 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

12 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

13 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

14 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

15 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

16 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

17 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C?12. What is the truth table of 1-bit magnitude comparator?

13. What is the use of magnitude comparator?

Expt.No.7: CODE CONVERSION

31 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Aim:

To design, construct and study the performance of 4-bit different code converters

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. Magnitude comparator IC 7485 2

6. EX-OR gate IC 7486 1

7. Connecting wires As required

Theory:

The availability of large variety of codes for the same discrete elements of information results in

the use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes the

two systems compatible even though each uses different binary code. The bit combination assigned to

binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs

and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0

and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a

circuit that makes the two systems compatible even though each uses a different binary code. To convert

from binary code to Excess-3 code, the input lines must supply the bit combination of elements as

specified by code and the output lines generate the corresponding bit combination of code. Each one of the

four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-

level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are

various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

Logic diagram:

32 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(i) Binary to gray code converter

Logic Diagram:

K map for G3:

G3 = B3

K map for G2:

K map for G1:

33 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for G0:

Truth table:

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

(ii) Gray to binary code converter

34 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Logic Diagram:

K map for B3:

B3=G3

K map for B2:

35 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K map for B1:

K map for B0:

Truth table:

36 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

(iii) BCD to excess-3 code converter

Logic Diagram:

K map for E3:

E3 = B3 + B2 (B0 + B1)

K map for E2:

37 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for E1:

K map for E0:

Truth table:

(iv) Excess-3 to

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x

38 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

BCD code converter

Logic Diagram:

K map for A:

A = X1 X2 + X3 X4 X1

K map for B:

39 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

K map for C:

K map for D:

Truth table:

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

40 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Procedure:

1. Connections were given as per circuit diagram.

2. Logical inputs were given as per truth table

3. Observe the logical output and verify with the truth tables.

Result:

Thus the code converters were designed and verified using the corresponding truth table.

Outcome:

At the completion of an experiment student will able to design the binary to gray converter.

1. What is binary code?

2. What is gray code?

3. What are the advantages of gray code?

4. What is unit distance code?

5. What is sequential code?

6. How to convert binary to gray code?

7. How to convert gray to binary code?

8. What is reflective code?

9. What are the advantages of EX ? 3 code?

10. Which code is used to arithmetic operation in digital circuits?

11. Explain the operation of EX ? OR.

12. What is K ? Map?

13. Draw the truth table of EX- OR gate.

14. What is SOP?

15. What is POS?

16. What is minterm?

Viva ? Voce

41 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Expt.No.8: PARITY GENERATORS AND CHECKERS

Aim:

To implement the odd and even parity checkers using the logic gates and also to generate the odd parity

and even parity numbers using the generators

Apparatus required:

Sl. No Component Type Quantity

1 Trainer Kit - 1

2 EX-OR IC7486 1

3 NOT gate IC 7404 1

4 Connecting wires - Required

Theory:

Parity checking is used for error detection in data transmission.

Odd parity checkers:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

odd.

Even parity checker:

It counts the number of 1?s in the given input and produces a 1 in the output when the number of 1?s is

even.

Odd parity generators:

It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also

the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits

which is an odd parity number.

Even parity generator:

It generates an even parity number. The even parity checker circuit is used with the inverted output and

also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5

bits which is an even parity number.

42 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

Truth table:

Input Checker output Generator output

A B C D D odd even odd even

0 0 0 1 1 0 00010 00011

0 0 1 0 1 0 00100 00101

0 0 1 1 0 1 00111 00110

0 1 0 0 1 0 01000 01001

0 1 0 1 0 1 01011 01010

0 1 1 0 0 1 01101 01100

0 1 1 1 1 0 01110 01111

1 0 0 0 1 0 10000 10001

1 0 0 1 0 1 10011 10010

1 0 1 0 0 1 10101 10100

1 0 1 1 1 0 10110 10111

1 1 0 0 0 1 11001 11000

1 1 0 1 1 0 11010 11011

1 1 1 0 1 0 11100 11101

1 1 1 1 0 1 11111 11110

Procedure:

1. The circuit is implemented using logic gates.

2. The inputs are given as per the truth table.

3. The corresponding outputs are noted.

4. The theoretical and practical values were verified.

Result:

The odd and even parity checkers are implemented using the logic gates and the odd parity and

even parity numbers are generated using the corresponding generators.

Outcome:

At the completion of an experiment student will able to verify the odd and even parity checker

using logic gates.

FirstRanker.com - FirstRanker's Choice

1 Format No.FirstRanker/stud/LM/34/issue:00/revision:00

?

DEPARTMENT OF

COMPUTER SCIENCE ENGINEERING

III SEMESTER - R 2017

CS8382 DIGITAL SYSTEMS LABORATORY

Name : _______________________________________

Register No : _______________________________________

Section : _______________________________________

LABORATORY MANUAL

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is committed to provide highly disciplined, conscientious and

enterprising professionals conforming to global standards through value based quality education and

training.

? To provide competent technical manpower capable of meeting requirements of the industry

? To contribute to the promotion of Academic Excellence in pursuit of Technical Education at different

levels

? To train the students to sell his brawn and brain to the highest bidder but to never put a price tag on

heart and soul

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

To provide candidates with knowledge and skill in the field of Electrical and Electronics

Engineering and thereby produce extremely well trained employable, socially responsible and innovative

Electrical and Electronics Engineers.

? To provide the students rigorous learning experience to produce creative solutions to society?s

needs.

? To produce electrical engineers of high calibre, conscious of the universal moral values adhering to

professional ethical code.

? To provide highest quality learning environment for the students emphasizing fundamental

concepts with strongly supported laboratory and prepare them to meet the global needs of the

industry by continuous assessment and training.

VISION

MISSION

VISION

MISSION

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PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. Fundamentals

To provide students with a solid foundation in mathematics, science and fundamentals of

engineering enabling them to solve complex problems in order to develop real time applications.

2. Core Competence

To train the students to meet the needs of core industry with an attitude of learning new

technologies.

3. Breadth

To provide relevant training and experience to bridge the gap between theory and practice which

enable them to find solutions to problems in industry and research that contributes to the overall

development of society.

4. Professionalism

To inculcate professional and effective communication skills to the students to make them lead a

team and stand as a good decision maker to manage any constraint environment with good

professional ethics at all strategies.

5. Lifelong Learning/Ethics

To practice ethical and professional responsibilities in the organization and society with

commitment and lifelong learning needed for successful professional career.

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PROGRAM OUTCOMES (POs)

a. Graduates will demonstrate knowledge of mathematics, science and electrical engineering.

b. Graduates will be able to identify, formulate and solve electrical engineering problems.

c. Graduates will be able to design and conduct experiments, analyze and interpret data.

d. Graduates will be able to design a system, component or process as per needs and specifications.

e. Graduates will demonstrate to visualize and work on laboratory and multidisciplinary tasks.

f. Graduates will demonstrate skills to use modern engineering tools, software and equipment to

analyze problems.

g. Graduates will demonstrate knowledge of professional and ethical responsibilities.

h. Graduates will be able to communicate effectively by both verbal and written form.

i. Graduates will show the understanding of impact of engineering solutions on the society and also

will be aware of contemporary issues.

j. Graduates will develop confidence for self-education and ability for lifelong learning.

k. Graduate who can participate and succeed in competitive examinations.

CS8381 DIGITAL SYSTEMS LABORATORY

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SYLLABUS

Objectives:

The student should be made to:

? Understand the various logic gates.

? Be familiar with various combinational circuits.

? Understand the various components used in the design of digital computers.

? Be exposed to sequential circuits

? Learn to use HDL

List of experiments:

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary

functions, code converters.

3. Design and implementation of combinational circuits using MSI devices:

a. 4 ? bit binary adder / subtractor

b. Parity generator / checker

c. Magnitude Comparator

d. Application using multiplexers

4. Design and implementation of sequential circuits:

a. Shift ?registers

b. Synchronous and asynchronous counters

5. Coding combinational / sequential circuits using HDL.

6. Design and implementation of a simple digital system (Mini Project).

Course Outcomes:

? Use Boolean simplification techniques to design a combinational hardware circuit.

? Design and Implement combinational and sequential circuits.

? Analyze a given digital circuit ? combinational and sequential.

? Design the different functional units in a digital computer system.

? Design and Implement a simple digital system.

CS8381 DIGITAL SYSTEMS LABORATORY

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Content

Sl.No. Name of the Experiment Page No.

1.

Verification of Boolean Theorems using Digital Logic Gates

2.

Design and Implementation of Combinational Circuits using Basic Gates for Arbitrary

Functions, Code Converters

3.

Implementation of half adder and full adder

4.

Implementation of half subtractor and full subtractor

5.

Design and Implementation of 4-Bit Binary Adder / Subtractor using Basic Gates and

MSI Devices

6.

Design and Implementation of Parity Generator / Checker using Basic Gates and MSI

Devices

7.

Design and Implementation of Magnitude Comparator.

8.

Design and Implementation of Application using Multiplexers / Demultiplexers.

9.

Design and Implementation of Shift Registers.

10.

Design and Implementation of Synchronous and Asynchronous Counters.

11.

Simulation of Combinational Circuits using Hardware Description Language (VHDL / Verilog

HDL Software Required).

12.

Simulation of Sequential Circuits using HDL (VHDL / Verilog HDL Software Required).

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Expt.No.1: STUDY OF BASIC GATES

Aim:

To verify the truth table of basic digital IC?s of AND, OR, NOT, NAND, NOR, EX-OR gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or

more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND gate

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs is

low.

OR gate

The OR gate performs a logical addition commonly known as OR function. The output is

high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT gate

A NOT gate is the physical realization of the complementation operation. The NOT gate is

called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND gate

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low

and any one of the input is low .The output is low level when both inputs are high.

NOR gate

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The

output is low when one or both inputs are high.

EX-OR gate

An Ex-OR gate performs the following Boolean function, A B = ( A . B? ) + ( A? . B ). It is

similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive

OR is a function that give an output signal ?0? when the two input signals are equal either ?0? or ?1?.

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AND Gate Symbol: PIN Diagram:

OR Gate:

OR GATE:

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NOT Gate symbol: PIN Diagram:

EXOR Gate symbol: PIN Diagram:

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NAND Gate symbol: PIN Diagram:

NOR Gate:

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Procedure:

1. Connections are given as per the circuit diagram.

2. For all the IC?s 7

th

pin is grounded and 14

th

pin is given +5 supply.

3. Apply the inputs and verify the truth table for all gates.

Result:

The truth tables of all the basic logic gates were verified.

Outcome:

At the completion of an experiment student will able to verify the truth

table of all basic gates

1. List out the basic gate.

2. Mention the universal gate.

3. How many gates presented in IC 7408?

4. What is IC?

5. What are the applications of gates?

6. Write the truth table of AND gate.

7. Write the truth table of OR gate.

8. Write the truth table of NOT gate.

9. Write the truth table of NAND gate.

10. Write the truth table of NOR gate.

11. Write the truth table of EX- OR gate.

12. What are the classifications of IC?

13. What are types of linear integrated circuit?

14. What is meant by etching?

15. What are the advantages of IC?

16. Write the truth table of EX- NOR gate.

Viva ? Voce

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Expt.No.2:

VERIFICATION OF BOOLEAN THEOREMS USING LOGIC

GATES

Aim: To verification of Boolean theorems using logic gates

Apparatus required:

Sl.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

6. NOR gate IC 7402 3

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Theory:

BASIC Boolean Laws

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A

2. A.B=B.A

2. Associative Law

The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C

2. A.(B.C) = (A.B).C

3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)

2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law

1. A+AB = A

2. A+AB =A+B

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5. Idempotent Law

1. A+A = A

2. A.A = A

6. Complementary Law

1. A+A' = 1

2. A.A' = 0

7. De Morgan ?s Theorem

1. The complement of the sum is equal to the sum of the product of the individual

complements.

A+B = A.B

2. The complement of the product is equal to the sum of the individual complements.

A.B = A+B

Design

1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A = A

3. Idempotent Law

1. A+A = A

2. A.A = A

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4. Demorgan ?s Law

A+B = A.B

5. Distributive Law

A+(B.C) = (A+B).(A+C)

Procedure:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to V

cc

.

3. Apply the inputs to the respective input pins.

4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

Outcome:

At the completion of an experiment student will able to know the basic laws with their truth table.

1. What is Demorgan?s law?

2. What is associative law?

3. What is mean by compliment gate?

4. Explain the basic laws in digital electronics

5. What is double complement?

Viva ? Voce

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Expt.No.3: HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits

Apparatus required:

S. No. Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. EX-OR gate IC 7486 1

6. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four

possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 (with 1 as carry)

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

Half adder:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented

with two half adders and one OR gate.

From the truth table, the expression for sum and carry bits of the output can be obtained as,

SUM = A?B?C + A?BC? + AB?C? + ABC

CARRY = A?BC + AB?C + ABC? +ABC

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Half Adder

Truth table:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum,

S = A B

Carry, C = A . B

Circuit diagram:

Full adder

Truth table:

Sl.No. Input Output

A B C S C

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

Sl.No. Input Output

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 1 1

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Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Sum:

SUM = A?B?C + A?BC? + AB?C?