Download JNTUH MCA 1st Sem R13 2018 January 811AB Computer Organization Question Paper

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Code No: 811AB

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R13

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

MCA I Semester Examinations, January - 2018

COMPUTER ORGANIZATION

Time: 3 Hours Max. Marks: 60

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Note:

This question paper contains two parts A and B.

Part A is compulsory which carries 20 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 8 marks and may have a, b, c as sub questions.

PART - A 5 x 4 Marks =20

1. What do you mean by an overflow in binary addition? How to detect the occurrence of an overflow? [4]

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2. What are the major storage levels in memory hierarchy? Why do we need a memory hierarchy? [4]
3. What are assembler directives? Explain the use of ‘DC’ and ‘DS’ in 8086. [4]
4. Explain the functionalities DMA control. [4]
5. Give hypercube structure for n = 3. [4]

PART -B 5 x 8 Marks =40

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1. a) Construct an 8-bit adder using full adders. [8]
2. b) Give the characteristic and excitation tables for SR and JK flip-flops. [4+4]
   OR
3. a) Give the internal logic circuit for4-1'multiplexer. [8]
4. b) Simplify the Boolean function AB'C + ABC'+ A'BC + AB'C' using k-map. [4+4]

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5. Explain associative memory hardware logic. [8]
   OR
6. a) If the cache access time is 100ns and memory access time is 500ns and the effective access time is 10% greater than the cache access time, what is the hit ratio? [8]
7. b) Give an overview of direct mapping cache assignment. [4+4]
8. Give an overview of INTEL 8086 program control instructions. [8]

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9. Give the sequence of actions performed on program ‘CALL’ and ‘RETURN". [4+4]
   OR
10. a) Explain how effective address is calculated in indexed addressing and relative addressing modes using examples. [8]
11. b) Write an assembly language program for computing the sum of » numbers. [4+4]
12. What is the need of input/output interface unit? Explain. [8]

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13. What are the different ways in which computer buses can be used to communicate with memory and I/O? [4+4]
    OR
14. a) Draw a flow chart that describes the CPU-IOP communication. [8]
15. b) Design parallel priority interrupt hardware for a system with eight interrupt sources. [4+4]
16. Instruction execution in a processor is divided into 5 stages- Instruction Fetch, Instruction Decode, Operand Fetch, Execute and Write Back. These stages take 5, 4, 20, 10 and 3 nanoseconds. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. What is the speed up achieved for 10 tasks? [8]

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17. Explain four possible hardware schemes that can be used in an instruction pipeline to minimize the performance degradation caused by instruction branching. [4+4]
    OR
18. What do you mean by memory interleaving? Explain how memory interleaving can be accomplished using modular memory organization. [8]