This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)
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Code: 9D06206b
Max. Marks: 60
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Time: 3 hours
M.Tech II Semester Supplementary Examinations January/February 2017
ALGORITHMS FOR VLSI DESIGN AUTOMATION
(Digital Systems & Computer Electronics)
Answer any FIVE questions
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All questions carry equal marks
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- List and explain any two design automation tools.
- How graph theory is useful for VLSI design automation.
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- Why combinational optimization is required? Explain the principle of backtracking.
- How combinatorial optimization is achieved using local & Tabu search.
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- Explain the concept of layout compaction bringing out clearly, how compaction is useful for VLSI design.
- Explain the routing problems in floor planning methods of VLSI design.
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- Explain how gate level modeling is inferior/superior to switch level modeling.
- Write about the compiler-driven simulation.
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- Explain the basic issues and terminology involved in logic synthesis and verification.
- Explain two-level logic synthesis with suitable examples.
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- How allocation, assignment and scheduling are done in high level synthesis?
- Explain high level transformations related to high level synthesis.
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- Explain the physical design cycle of FPGA.
- Explain about partitioning for segmented models.
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- Explain briefly:
- MCM physical design cycle.
- Maze routing.
- Programmable MCM.
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This download link is referred from the post: JNTUA M.Tech 2nd Sem last 10 year 2010-2020 Previous Question Papers (JNTU Anantapur)