PTU B.Tech 3D EEE 4th Semester May 2019 57103 DIGITAL ELECTRONICS Question Papers

PTU Punjab Technical University B-Tech May 2019 Question Papers 4th Semester Electrical and Electronics Engineering (EEE)-EE-Electrical Engineering

Roll No.
Total No. of Pages : 02
Total No. of Questions : 09
B.Tech.(EE)/(Electrical & Electronics)/(Electronics & Electrical)(2011 onwards)
B.Tech.(Electrical Engineering & Industrial Control) (2012 Onwards)
(Sem.?4)
DIGITAL ELECTRONICS
Subject Code : BTEC-404
M.Code : 57103
Time : 3 Hrs. Max. Marks : 60
INSTRUCTION TO CANDIDATES :
1.
SECTION-A is COMPULSORY consisting of TEN questions carrying T WO marks
each.
2.
SECTION-B contains FIVE questions carrying FIVE marks each and students
has to attempt any FOUR questions.
3.
SECTION-C contains T HREE questions carrying T EN marks each and students
has to attempt any T WO questions.

SECTION-A
1.
Answer briefly :

a) Convert (101110)2 to hexadecimal and octal number.

b) Express 10101100 BCD code into gray code.

c) Define the race around condition in flip flop.

d) Draw the logic diagram of half adder.

e) State any two applications of shift register.

f) Why TTL is preferred over DTL?

g) What do you mean by priority encoder?

h) Compare the function of decoder and encoder.

i) What is the advantage of the R-2R ladder DAC over the weighted resister type DAC?

j) Draw CMOS circuit for NOR gate.
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SECTION-B
2.
Implement Y ( A C)( A D) ( A B C) using NOR gates only.
3.
Simplify using Boolean laws and draw the logic diagram for the given expression.
F ABC ABC ABC ABC ABC
4.
Minimize the following function using K-map
F (A, B, C, D)
m (0,1, 7,8,13,15) (2, 6,10,11)


5.
Explain the Master-slave JK flip-flop with the help of circuit diagram and waveforms
6.
Explain the different modeling styles in VHDL with suitable examples.

SECTION-C
7.
a) Use a 8 ? 1 MUX to implement the logic function
F
m (0,1, 2, 3, 4,10,11,14,15)



b) Draw and explain the working of a synchronous mod-3 counter.
8.
a) Compare TTL, ECL, RTL, DCTL and DTL w.r.t. fan-in, fan-out and noise margin.

b) An 8-bit successive approximation converter (SAC) has a resolution of 15mV. What

will its digital output be for an analog input of 2.65 V?
9.
Write short notes on Any Two :

a) PLD

b) Ring Counters

c) Demultiplexers

NOTE : Disclosure of Identity by writing Mobile No. or Making of passing request on any
page of Answer Sheet will lead to UMC against the Student.
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